Patents by Inventor Ernest Knol

Ernest Knol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock distribution phase alignment technique
    Patent number: 6630855
    Abstract: A phase alignment technique includes providing a clock signal to a first clock distribution spine and providing at least one additional clock distribution spine. One PLL (Phase Locked Loop) is provided for each additional clock distribution spine, each PLL having an REF input and an FBK input and an output. The REF input of each PLL is connected to the first clock distribution spine and the FBK input of each PLL is connected to its respective clock distribution spine and the output of each PLL is connected to its respective clock distribution spine to provide a clock signal thereto. Each PLL provides phase alignment between the clock signal on the first clock distribution spine and the clock signal outputted by the PLL to its respective clock distribution spine. The first clock distribution spine and each additional clock distribution spine and its respective PLL may be disposed on an integrated circuit die.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: October 7, 2003
    Assignee: Intel Corporation
    Inventors: Eyal Fayneh, Ernest Knol
  • Clock distribution phase alignment technique
    Publication number: 20020140487
    Abstract: A phase alignment technique includes providing a clock signal to a first clock distribution spine and providing at least one additional clock distribution spine. One PLL (Phase Locked Loop) is provided for each additional clock distribution spine, each PLL having an REF input and an FBK input and an output. The REF input of each PLL is connected to the first clock distribution spine and the FBK input of each PLL is connected to its respective clock distribution spine and the output of each PLL is connected to its respective clock distribution spine to provide a clock signal thereto. Each PLL provides phase alignment between the clock signal on the first clock distribution spine and the clock signal outputted by the PLL to its respective clock distribution spine. The first clock distribution spine and each additional clock distribution spine and its respective PLL may be disposed on an integrated circuit die.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 3, 2002
    Inventors: Eyal Fayneh, Ernest Knol