Patents by Inventor Ernest Knoll
Ernest Knoll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11927612Abstract: A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal, and is comprised of delay elements having a first threshold voltage. A second delay line outputs a second delayed signal, and is comprised of delay elements having a second threshold voltage that is higher than the first threshold voltage. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.Type: GrantFiled: October 19, 2022Date of Patent: March 12, 2024Assignee: Marvell Asia Pte LtdInventors: Ernest Knoll, Omer Yassur
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Publication number: 20220091168Abstract: An apparatus comprising a frequency monitor circuitry to receive a first clock signal, a second clock signal and an expected frequency ratio, determine whether a ratio between the first clock signal and the second clock signal matches an expected an expected frequency ratio and generate an error signal upon a determination that the ratio between the first clock signal and the second clock signal does not match the expected frequency ratio.Type: ApplicationFiled: December 7, 2021Publication date: March 24, 2022Applicant: Intel CorporationInventors: Yossi Ben Simon, Ido Kahan, Ofir Shwartz, Ernest Knoll, Assaf Admoni
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Publication number: 20220083093Abstract: Techniques and mechanisms for determining an amount of skew between two clock signals. In an embodiment, detector circuitry receives a first signal and a signal which indicate (respectively) a NAND combination of clock signals, and a NOR combination of the clock signals. The detector circuitry evaluates a first length of time that the first signal indicates a respective first logic state, and a second length of time that the second signal indicates a respective second logic state. The skew is calculated based on a difference between the first length of time and the second length of time. In another embodiment, one of the first signal or the second signal is generated with a combinatorial logic gate, a transistor of which is relatively large, as compared to another transistor which is to operate based on one of the first signal, the second signal, or the clock signals.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Applicant: Intel CorporationInventors: Yossi Ben Simon, Ariel Avital, Arkady Vaisman, Ernest Knoll
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Patent number: 10958278Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.Type: GrantFiled: July 31, 2019Date of Patent: March 23, 2021Assignee: Intel CorporationInventors: Ariel Gur, Daniel J. Ragland, Yoav Ben-Raphael, Ernest Knoll
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Publication number: 20210036708Abstract: Embodiments of the present disclosure describe methods, apparatuses, and systems for phase-lock loop (PLL) configuration and realization to provide various reference clock frequencies to computing core(s) and processor(s), and other benefits. A post digitally-controlled oscillator (DCO) divider (PDIV) of the PLL may be configured with a dedicated PDIV threshold value corresponding to a dedicated target reference frequency.Type: ApplicationFiled: July 31, 2019Publication date: February 4, 2021Inventors: Ariel Gur, Daniel J. Ragland, Yoav Ben-Raphael, Ernest Knoll
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Publication number: 20170149554Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.Type: ApplicationFiled: November 24, 2015Publication date: May 25, 2017Applicant: Intel CorporationInventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
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Patent number: 9660799Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.Type: GrantFiled: November 24, 2015Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Alexander Gendler, Ernest Knoll, Ofer Nathan, Michael Mishaeli, Krishnakanth V. Sistla, Ariel Sabba, Shani Rehana, Ariel Szapiro, Tsvika Kurts, Ofer Levy
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Patent number: 7605668Abstract: Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.Type: GrantFiled: December 12, 2006Date of Patent: October 20, 2009Assignee: Intel CorporationInventors: Eyal Fayneh, Ernest Knoll
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Publication number: 20080157880Abstract: Disclosed herein are embodiments of a temperature compensating solution to reduce changes in PLL damping factor that would otherwise occur with changes in temperature.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Eyal Fayneh, Ernest Knoll
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Publication number: 20080150596Abstract: Disclosed herein are embodiments of a charge pump that can provide an output voltage with an output current that remains sufficiently constant over an operating range of the output voltageType: ApplicationFiled: December 22, 2006Publication date: June 26, 2008Inventors: Eyal Fayneh, Ernest Knoll
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Publication number: 20080136545Abstract: Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.Type: ApplicationFiled: December 12, 2006Publication date: June 12, 2008Inventors: Eyal Fayneh, Ernest Knoll
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Patent number: 7363523Abstract: An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C4) state, and the processor may quickly exit to a C2 state in response to a bus event such as a bus snoop.Type: GrantFiled: August 31, 2004Date of Patent: April 22, 2008Assignee: Intel CorporationInventors: Tsvika Kurts, Alon Naveh, Efraim Rotem, Brad M. Dendinger, Jorge P. Rodriguez, Ernest Knoll, David I. Poisner
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Patent number: 7265637Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.Type: GrantFiled: June 29, 2006Date of Patent: September 4, 2007Assignee: Intel CorporationInventors: Ernest Knoll, Eyal Fayneh
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Publication number: 20060244542Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.Type: ApplicationFiled: June 29, 2006Publication date: November 2, 2006Inventors: Ernest Knoll, Eyal Fayneh
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Patent number: 7120839Abstract: A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than +/?1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.Type: GrantFiled: August 22, 2003Date of Patent: October 10, 2006Assignee: Intel CorporationInventors: Eyal Fayneh, Ernest Knoll
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Patent number: 7095289Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.Type: GrantFiled: May 5, 2005Date of Patent: August 22, 2006Assignee: Intel CorporationInventors: Ernest Knoll, Eyal Fayneh
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Publication number: 20060047986Abstract: An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C4) state, and the processor may quickly exit to a C2 state in response to a bus event such as a bus snoop.Type: ApplicationFiled: August 31, 2004Publication date: March 2, 2006Inventors: Tsvika Kurts, Alon Naveh, Efraim Rotem, Brad Dendinger, Jorge Rodriguez, Ernest Knoll, David Poisner
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Publication number: 20050206459Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.Type: ApplicationFiled: May 5, 2005Publication date: September 22, 2005Inventors: Ernest Knoll, Eyal Fayneh
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Patent number: 6922047Abstract: An apparatus for controlling a phase-locked loop includes a detector for detecting at least one of a startup condition and a yank condition and a controller for controlling current between a charge pump and the phase-locked loop. If a startup condition is detected, the controller sinks current from a control node connected to a loop filter of the phase-locked loop. This, in turn, causes a bias voltage to increase until the phase-locked loop transitions from startup mode to a normal acquisition mode. The current sink is provided by a dummy charge pump and the startup condition is determined by detecting the end of a PLL disable state. If a yank condition is detected, a charge pump connected to a phase-frequency detector of the phase-locked loop controls the bias voltage until a feedback frequency becomes lower than a reference frequency. Methods for controlling a phase-locked loop during both modes of operation may use of the aforementioned apparatus.Type: GrantFiled: May 29, 2003Date of Patent: July 26, 2005Assignee: Intel CorporationInventors: Ernest Knoll, Eyal Fayneh
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Patent number: 6914490Abstract: A method for controlling a phase-locked loop includes receiving a frequency change signal and electrically isolating a VCO control node of the phase-locked loop from at least one charge pump of the loop. During this isolation period, the VCO control node voltage is held at a constant value equal to the voltage that existed before the frequency change signal was received. One or more parameters of the PLL are then altered in a manner that will ensure generation of a newly desired output frequency. These parameters include but are not limited to a feedback divider value and a reference frequency input into the PLL. The new output frequency may be above or below the pre-change signal frequency depending, for example, on a mode of operation of a host system. When the VCO control node is once again electrically connected to the charge pump, the PLL locks on to the desired output frequency.Type: GrantFiled: May 29, 2003Date of Patent: July 5, 2005Assignee: Ibtel CorporationInventors: Eyal Fayneh, Ernest Knoll