Patents by Inventor Ernest L. Edgar
Ernest L. Edgar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240020216Abstract: A trace circuitry may be configured to receive a selection of one or more types of events possible in a processor core among multiple types of events. The trace circuitry may generate a message including trace information when an event corresponding to the selection occurs in the processor core. The trace information may include an address associated with the event and an indication of the type of event and/or cause for why the event occurred. In some implementations, the trace circuitry may use an event filter to pass events corresponding to the one or more types of events that are selected and block events corresponding to one or more types of events that are not selected. In some implementations, the trace circuitry may generate timestamps based on events to enable measurements between the events.Type: ApplicationFiled: March 20, 2023Publication date: January 18, 2024Inventors: Bruce Ableidinger, Ernest L. Edgar
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Patent number: 11675945Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: May 2, 2022Date of Patent: June 13, 2023Assignee: SiFive, Inc.Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Publication number: 20220308878Abstract: A trace encoder may be connected to a processor core. The trace encoder may be configured to maintain a count of branches that are consecutively taken when executed by the processor core and/or a count of branches that are consecutively not-taken when executed by the processor core. The trace encoder may be configured to send a message including the count.Type: ApplicationFiled: March 18, 2022Publication date: September 29, 2022Inventors: Bruce Ableidinger, Ernest L. Edgar
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Publication number: 20220261522Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: ApplicationFiled: May 2, 2022Publication date: August 18, 2022Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Patent number: 11321511Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: GrantFiled: January 25, 2021Date of Patent: May 3, 2022Assignee: SiFive, Inc.Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Publication number: 20210173987Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains and reset crossings between reset domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. Reset crossings may be automatically generated in a similar manner. For example, implicit classes may be used to generate clock crossings or reset crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.Type: ApplicationFiled: January 25, 2021Publication date: June 10, 2021Inventors: Henry Cook, Ernest L. Edgar, Ryan Macdonald, Wesley Waylon Terpstra
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Patent number: 8185879Abstract: A method for tracing a multi-tasking embedded pipelined processor includes executing compiled code including trace controls. Tracing is initiated when the execution of the compiled code is initiated. Tracing is stopped when execution of the compiled code is completed. A trace record is formed during tracing. The trace record includes a processor mode indication, application space identity value and an instruction architecture set mode indication.Type: GrantFiled: November 6, 2006Date of Patent: May 22, 2012Assignee: MIPS Technologies, Inc.Inventors: Radhika Thekkath, Franz Treue, Ernest L. Edgar, Richard T. Leatherman
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Patent number: 7886150Abstract: An embedded system or system on chip (SoC) includes a secure JTAG system and method to provide secure on-chip control, capture, and export of on chip information in an embedded environment to a probe. In one embodiment, the system comprises encryption logic associated with a JTAG subsystem and decryption logic in the probe for encrypted JTAG read traffic. Inverted encryption/decryption logic provides bi-directional encryption and decryption of JTAG traffic. Encrypted information includes both authentication of valid probe/target interface and encryption of debug data.Type: GrantFiled: May 11, 2007Date of Patent: February 8, 2011Assignee: MIPS Technologies, Inc.Inventors: Neal S. Stollon, Ernest L. Edgar
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Patent number: 7702055Abstract: A method of tracing processor data includes receiving a first trace stream from a first processor operating in response to a first clock and a second trace stream from a second processor operating in response to a second clock. The first trace stream is routed to a first dual-port synchronous memory in accordance with the first clock and the second trace stream is routed to a second dual-port synchronous memory in accordance with the second clock. The first trace stream and the second trace stream are delivered to a memory in accordance with a third clock.Type: GrantFiled: September 29, 2006Date of Patent: April 20, 2010Assignee: MIPS Technologies, Inc.Inventor: Ernest L. Edgar
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Publication number: 20090037886Abstract: A system includes a processor to generate a free-running trace stream and a probe with a real-time decoder to dynamically detect a trigger included in the free-running trace stream.Type: ApplicationFiled: July 30, 2007Publication date: February 5, 2009Applicant: MIPS TECHNOLOGIES, INC.Inventors: Scott M. MCCOY, Ernest L. EDGAR, Bruce J. ABLEIDINGER
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Publication number: 20080282087Abstract: An embedded system or system on chip (SoC) includes a secure JTAG system and method to provide secure on-chip control, capture, and export of on chip information in an embedded environment to a probe. In one embodiment, the system comprises encryption logic associated with a JTAG subsystem and decryption logic in the probe for encrypted JTAG read traffic. Inverted encryption/decryption logic provides bi-directional encryption and decryption of JTAG traffic. Encrypted information includes both authentication of valid probe/target interface and encryption of debug data.Type: ApplicationFiled: May 11, 2007Publication date: November 13, 2008Applicant: MIPS TECHNOLOGIES, INC.Inventors: Neal S. Stollon, Ernest L. Edgar
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Publication number: 20080155345Abstract: A method of monitoring bus transactions between masters and slaves includes generating simplified bus transaction descriptors to characterize bus transactions. Simplified bus transaction descriptors are consolidated to form a bus transaction trace stream. The bus transaction trace stream is routed to a probe.Type: ApplicationFiled: October 31, 2006Publication date: June 26, 2008Applicant: MIPS TECHNOLOGIES, INC.Inventors: Ernest L. EDGAR, Bruce ABLEIDINGER, Neal S. STOLLON
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Publication number: 20080080651Abstract: A method of tracing processor data includes receiving a first trace stream from a first processor operating in response to a first clock and a second trace stream from a second processor operating in response to a second clock. The first trace stream is routed to a first dual-port synchronous memory in accordance with the first clock and the second trace stream is routed to a second dual-port synchronous memory in accordance with the second clock. The first trace stream and the second trace stream are delivered to a memory in accordance with a third clock.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Applicant: MIPS Technologies, Inc.Inventor: Ernest L. Edgar
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Publication number: 20080082801Abstract: A method of tracing processor instructions includes characterizing processor state changes in accordance with simplified instruction state descriptors. The simplified instruction state descriptors are then traced with processor instructions, but processor data is not traced.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Applicant: MIPS Technologies, Inc.Inventors: Ernest L. EDGAR, Radhika Thekkath
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Patent number: 7134116Abstract: A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.Type: GrantFiled: April 30, 2001Date of Patent: November 7, 2006Assignee: MIPS Technologies, Inc.Inventors: Radhika Thekkath, Franz Treue, Ernest L. Edgar, Richard T. Leatherman
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Patent number: 7043668Abstract: A system and method for program counter and data tracing is disclosed. Generated trace messages are included within a trace word format and stored in trace memory, thereby enabling a reduction in the amount of trace storage required.Type: GrantFiled: June 29, 2001Date of Patent: May 9, 2006Assignee: MIPS Technologies, Inc.Inventors: Franz Treue, Radhika Thekkath, Ernest L. Edgar, Richard T. Leatherman