Patents by Inventor Ernest Li
Ernest Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9780164Abstract: A silicon-on-insulator radio frequency device and a silicon-on-insulator substrate are provided. In the silicon-on-insulator radio frequency device, a pit is formed on a surface of a high resistivity silicon plate which is close to a buried oxide layer. The pit may be filled with an insulating material, thereby increasing an equivalent surface resistance of the high resistivity silicon plate; or no insulating material is filled into the pit, that is, the pit remains a vacuum state or is only filled with air, which can increase the equivalent surface resistance of the high resistivity silicon plate as well. In such, an eddy current generated on a surface of the high resistivity silicon plate under the action of a radio frequency signal may be reduced. As a result, loss of the radio frequency signal is reduced and the linearity of the radio frequency signal is improved.Type: GrantFiled: December 19, 2013Date of Patent: October 3, 2017Assignee: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventors: Ernest Li, Daniel Xu
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Patent number: 9299601Abstract: A SOI RF device and a method for forming the same are provided. A trench exposed a part of the high resistivity silicon base is formed in the SOI substrate; a non-doped polysilicon layer is disposed on the high resistivity silicon base which is exposed by the trench; and at least a part of the non-doped polysilicon layer is covered by an above metal layer. With effects of the metal layer which is applied with a RF signal or a superposed signal, and fixed charges in the BOX layer, an inversion layer may be formed at a surface of the non-doped polysilicon layer. Since carriers may easily recombine at the grain boundaries of polysilicon, eddy current generated on a surface of the high resistivity silicon base is reduced, loss of the RF signal is reduced, and linearity of the RF signal device is improved.Type: GrantFiled: January 21, 2014Date of Patent: March 29, 2016Assignee: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventor: Ernest Li
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Patent number: 9230855Abstract: An interconnect structure and a forming method thereof are provided. The method includes: providing a semiconductor substrate which has semiconductor devices formed therein; forming a conductive layer on the semiconductor substrate; forming a mask layer on the conductive layer; forming a groove in the mask layer and the conductive layer, the groove having a depth-to-width ratio greater than 0.8; and depositing an intermetallic dielectric layer to cover the mask layer and fill the groove, wherein an air gap is formed in a portion of the intermetallic dielectric layer in the groove. The mask layer is formed on the conductive layer, so that the depth-to-width ratio of the groove between adjacent interconnects is increased. Besides, the air gap with a relatively large size is formed between two adjacent interconnects. Therefore, a dielectric constant and parasitic capacitance between adjacent interconnects are reduced evidently, and the performance of the semiconductor devices is improved.Type: GrantFiled: December 17, 2013Date of Patent: January 5, 2016Assignee: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventor: Ernest Li
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Publication number: 20140357051Abstract: A method for forming a radio frequency device is provided. The method may include: providing a semiconductor-on-insulator layer, which comprises a back substrate, a buried oxide layer and a top semiconductor layer, where a plurality of transistors and an interlayer dielectric layer covering the plurality of transistors are formed on a surface of the top semiconductor layer; providing a temporary supporting layer having a smooth surface, and adhering a surface of the interlayer dielectric layer to the temporary supporting layer; removing the back substrate to expose the buried oxide; providing a high resistivity substrate, and adhering the high resistivity substrate to the buried oxide layer; and removing the temporary supporting layer to expose the surface of the interlayer dielectric layer after the high resistivity substrate and the buried oxide layer is adhered. Signal loss of the radio frequency devices may be reduced, and signal linearity is improved.Type: ApplicationFiled: January 16, 2014Publication date: December 4, 2014Applicant: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventor: Ernest Li
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Publication number: 20140242792Abstract: A method for forming a semiconductor device is provided, which may include: providing an interlayer dielectric layer, a metal layer formed on the interlayer dielectric layer, an etch stop layer formed on the metal layer, and a first opening extending through the etch stop layer and the metal layer, wherein the interlayer dielectric layer is exposed from the first opening; forming a protecting layer on the sidewall of the first opening to cover the metal layer; after forming the protecting layer, forming a second opening by etching a portion of the interlayer dielectric layer; and forming an isolating layer by filling up the second opening, wherein the isolating layer includes an air gap. The semiconductor device is more stable in performance.Type: ApplicationFiled: December 26, 2013Publication date: August 28, 2014Applicant: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATIONInventors: Zhangli LIU, Ernest LI
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Publication number: 20140210038Abstract: A SOI RF device and a method for forming the same are provided. A trench exposed a part of the high resistivity silicon base is formed in the SOI substrate; a non-doped polysilicon layer is disposed on the high resistivity silicon base which is exposed by the trench; and at least a part of the non-doped polysilicon layer is covered by an above metal layer. With effects of the metal layer which is applied with a RF signal or a superposed signal, and fixed charges in the BOX layer, an inversion layer may be formed at a surface of the non-doped polysilicon layer. Since carriers may easily recombine at the grain boundaries of polysilicon, eddy current generated on a surface of the high resistivity silicon base is reduced, loss of the RF signal is reduced, and linearity of the RF signal device is improved.Type: ApplicationFiled: January 21, 2014Publication date: July 31, 2014Applicant: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventor: Ernest Li
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Publication number: 20140175598Abstract: A silicon-on-insulator radio frequency device and a silicon-on-insulator substrate are provided. In the silicon-on-insulator radio frequency device, a pit is formed on a surface of a high resistivity silicon plate which is close to a buried oxide layer. The pit may be filled with an insulating material, thereby increasing an equivalent surface resistance of the high resistivity silicon plate; or no insulating material is filled into the pit, that is, the pit remains a vacuum state or is only filled with air, which can increase the equivalent surface resistance of the high resistivity silicon plate as well. In such, an eddy current generated on a surface of the high resistivity silicon plate under the action of a radio frequency signal may be reduced. As a result, loss of the radio frequency signal is reduced and the linearity of the radio frequency signal is improved.Type: ApplicationFiled: December 19, 2013Publication date: June 26, 2014Applicant: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventors: Ernest Li, Daniel Xu
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Publication number: 20140167271Abstract: An interconnect structure and a forming method thereof are provided. The method includes: providing a semiconductor substrate which has semiconductor devices formed therein; forming a conductive layer on the semiconductor substrate; forming a mask layer on the conductive layer; forming a groove in the mask layer and the conductive layer, the groove having a depth-to-width ratio greater than 0.8; and depositing an intermetallic dielectric layer to cover the mask layer and fill the groove, wherein an air gap is formed in a portion of the intermetallic dielectric layer in the groove. The mask layer is formed on the conductive layer, so that the depth-to-width ratio of the groove between adjacent interconnects is increased. Besides, the air gap with a relatively large size is formed between two adjacent interconnects. Therefore, a dielectric constant and parasitic capacitance between adjacent interconnects are reduced evidently, and the performance of the semiconductor devices is improved.Type: ApplicationFiled: December 17, 2013Publication date: June 19, 2014Applicant: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventor: Ernest Li
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Publication number: 20140167284Abstract: An interconnect structure and a forming method thereof are provided. The method includes: providing a semiconductor substrate which has semiconductor devices formed therein; forming an interlayer dielectric layer on the semiconductor substrate; forming a conductive layer on the interlayer dielectric layer; forming a groove in the conductive layer and the interlayer dielectric layer, the groove having a depth smaller than a sum of a thickness of the conductive layer and a thickness of the interlayer dielectric layer and having a depth-to-width ratio greater than 0.8; and depositing an intermetallic dielectric layer to cover the conductive layer and fill the groove, and forming an air gap in the intermetallic dielectric layer in the groove. The depth-to-width ratio of the groove and a size of the air gap are increased. Therefore, parasitic capacitance between the adjacent interconnects is reduced, and the performance of the semiconductor devices is improved.Type: ApplicationFiled: September 25, 2013Publication date: June 19, 2014Applicant: Grace Semiconductor Manufacturing CorporationInventor: Ernest Li