Patents by Inventor Ernest N. Levine
Ernest N. Levine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7034400Abstract: A metallization insulating structure, having a substrate; a substantially fluorine free insulating layer formed on the substrate, having a height, hi; a fluorine containing insulating layer formed on the substantially fluorine free insulating layer, having a height hf.Type: GrantFiled: September 10, 2003Date of Patent: April 25, 2006Assignee: International Business Machines CorporationInventors: Edward P. Barth, Glenn A. Biery, Jeffrey P. Gambino, Thomas H. Ivers, Hyun K. Lee, Ernest N. Levine, Ann McDonald, Anthony K. Stamper
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Publication number: 20040061235Abstract: A metallization insulating structure, havingType: ApplicationFiled: September 10, 2003Publication date: April 1, 2004Inventors: Edward P. Barth, Glenn A. Biery, Jeffrey P. Gambino, Thomas H. Ivers, Hyun K. Lee, Ernest N. Levine, Ann McDonald, Anthony K. Stamper
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Publication number: 20020076917Abstract: A metallization insulating structure, havingType: ApplicationFiled: December 20, 1999Publication date: June 20, 2002Inventors: EDWARD P BARTH, GLENN A BIERY, JEFFREY P GAMBINO, THOMAS H IVERS, HYUN K LEE, ERNEST N LEVINE, ANN MCDONALD, ANTHONY K STAMPER
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Publication number: 20020017726Abstract: A metal layer is formed at high deposition rate over severe topography by a two step process including formation of a seed layer by cold deposition followed by a second portion of the metal layer deposited at a temperature approximating but below a temperature at which metal from a lower metal layer can extrude through vias reaching thereto. The seed layer is preferably limited to a thickness at which the conformality of the cold-deposited metal will not significantly increase severity of surface topography, generally about one-fourth the thickness of the hot-deposited layer. Via connections are formed without voids and a more planar metal layer surface is formed which allows formation of a protective/anti-reflective layer with good integrity while enhancing subsequent lithographic patterning, thereby eliminating alteration of metal surface chemistry by resist developers and resultant residual metal included within the severe topography.Type: ApplicationFiled: February 25, 2000Publication date: February 14, 2002Inventors: Parth P. Dave, Nancy A. Greco, Ernest N. Levine, Darryl D. Restaino
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Patent number: 6335151Abstract: A lithographic process for creation and replication of well-controlled surfaces of arbitrary profiles on a sub-micron scale. The surfaces are defined by a mathematical function using a binary mask, consisting partly or wholly of subresolution features, and a photoresist film of pre-specified absorption and thickness. The process comprises the steps of (a) creating a mask, (b) imaging the mask pattern on an absorbing photoresist film to a predetermined thickness, and (c) transferring the three dimensional surface to a substrate.Type: GrantFiled: June 18, 1999Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: Christopher P. Ausschnitt, Nancy Greco, Ernest N. Levine
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Patent number: 6177348Abstract: A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.Type: GrantFiled: January 20, 1998Date of Patent: January 23, 2001Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Peter D. Hoh, Mark A. Jaso, Ernest N. Levine
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Patent number: 6174814Abstract: The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.Type: GrantFiled: April 25, 2000Date of Patent: January 16, 2001Assignee: International Business Machines CorporationInventors: Robert F. Cook, Eduardo Garcia, Nancy A. Greco, Stephen E. Greco, Ernest N. Levine
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Patent number: 6091131Abstract: The propagation of a crack from the surface of the dielectric layer of an integrated circuit, through to the underlying circuit elements, is prevented by controlling the interface between the outermost, dielectric layer or layers and the inner layer or layers of the integrated circuit construction. The interface is weakened so that a crack that encounters the interface is caused to propagate in a horizontal manner, along the interface, preventing propagation of the crack in a direction that would be harmful to the manufactured article. This is preferably accomplished with multiple layers of material, each of which is made capable of redirecting (deflecting) the crack. Deflection of the crack, and arrest of the deflected crack along the interface, is made possible by controlling the fracture resistance of the interface.Type: GrantFiled: April 28, 1998Date of Patent: July 18, 2000Assignee: International Business Machines CorporationInventors: Robert F. Cook, Eduardo Garcia, Nancy A. Greco, Stephen E. Greco, Ernest N. Levine
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Patent number: 6083823Abstract: A metal layer is formed at high deposition rate over severe topography by a two step process including formation of a seed layer by cold deposition followed by a second portion of the metal layer deposited at a temperature approximating but below a temperature at which metal from a lower metal layer can extrude through vias reaching thereto. The seed layer is preferably limited to a thickness at which the conformality of the cold-deposited metal will not significantly increase severity of surface topography, generally about one-fourth the thickness of the hot-deposited layer. Via connections are formed without voids and a more planar metal layer surface is formed which allows formation of a protective/anti-reflective layer with good integrity while enhancing subsequent lithographic patterning, thereby eliminating alteration of metal surface chemistry by resist developers and resultant residual metal included within the severe topography.Type: GrantFiled: June 28, 1996Date of Patent: July 4, 2000Assignee: International Business Machines CorporationInventors: Parth P. Dave, Nancy A. Greco, Ernest N. Levine, Darryl D. Restaino
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Patent number: 5834829Abstract: An energy relieving, redundant crack stop and the method of producing the same is disclosed. The redundant pattern allows the crack propagating energy that is not absorbed by the first ring of metallization to be absorbed by a second area of metallization and also provides a greater surface area over which the crack producing energy may be spread. The redundant crack stop is produced during the metallization process along with the rest of the wiring of the chip surface and, therefore, no additional production steps are necessary to form the structure.Type: GrantFiled: September 5, 1996Date of Patent: November 10, 1998Assignees: International Business Machines Corporation, Siemens Components, Inc.Inventors: Bettina A. Dinkel, Pei-Ing Lee, Ernest N. Levine
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Process for forming improved solder connections for semiconductor devices with enhanced fatigue life
Patent number: 4611746Abstract: In accordance with the present invention, we provide a new method for relieving stresses in the device-substrate interconnection structure which greatly enhances the resistance of the interconnection solder bonds to fatigue failure. In accordance with the aforementioned object of the process of our invention for forming improved solder interconnections between integrated circuit semiconductor devices and the supporting substrate, the process includes the step of joining the device I/O pads to the corresponding I/O pads of the substrate by positioning the device over the substrate with solder material selectively positioned between the respective I/O pads, heating the assembly to at least the melting point of the solder material, and cooling to solidify the solder. Subsequently, the resultant device-substrate is annealed by heating to an annealing temperature in the range of 115.degree. to 135.degree. C. and maintaining this temperature for a time in excess of 2 days.Type: GrantFiled: June 28, 1984Date of Patent: September 16, 1986Assignee: International Business Machines CorporationInventors: Ernest N. Levine, Lewis D. Lipschutz, Horatio Quinones -
Patent number: 4256949Abstract: A combination of welding wire and welding flux for submerged arc welding of high strength low alloy pipe which require low temperature impact properties of at least 30 ft./lb. at -13.degree. F. The wire consists essentially of 2.0 to 3.5 wt. % manganese; 0.01 wt. % to 1.5 wt. % silicon; 0.05 to 0.15 wt. % carbon; balance iron with the proviso that when manganese is greater than 2.5 up to 3.5 wt. % the silicon content is between 0.01 wt. % to 1.5 wt. % and when the manganese content is between 2.0 to 2.5 wt. % the silicon content is greater than 0.3 wt. % up to 1.5 wt. %. The flux used with these wires is preferably acidic in nature.Type: GrantFiled: March 27, 1979Date of Patent: March 17, 1981Assignee: Union Carbide CorporationInventors: Stephen F. Baumann, Masahiro Nakabayashi, Gerald D. Uttrachi, Thomas L. Coless, Ernest N. Levine