Abstract: When a media error occurs on a storage device of a number of storage devices of a redundant array, the logical stripe of data affected by the media error is determined. A portion of non-volatile memory is reserved and the logical stripe is backed up to this portion of non-volatile memory. A read request is subsequently serviced from the non-volatile memory and not from the storage devices. When a write request is received, it is first serviced to the storage devices. If successful, then the previously reserved portion of non-volatile memory is freed up, and subsequent requests are serviced using the storage devices. If unsuccessful, then the write request is serviced using the non-volatile memory.

Abstract: When a media error occurs on a storage device of a number of storage devices of a redundant array, the logical stripe of data affected by the media error is determined. A portion of non-volatile memory is reserved and the logical stripe is backed up to this portion of non-volatile memory. A read request is subsequently serviced from the non-volatile memory and not from the storage devices. When a write request is received, it is first serviced to the storage devices. If successful, then the previously reserved portion of non-volatile memory is freed up, and subsequent requests are serviced using the storage devices. If unsuccessful, then the write request is serviced using the non-volatile memory.

Abstract: Multiple PCI adapter cards are supported by a single PCI slot through the aspects of the present invention. A computer system aspect includes an &mgr;ATX planar including at least one PCI slot, and a riser card mounted in the at least one PCI slot, the riser card supporting multiple PCI adapter cards and providing signal generation to allow the multiple PCI adapter cards to utilize the at least one PCI slot. The riser card aspect includes a PCI connector for coupling to a PCI slot on the &mgr;ATX planar, a plurality of PCI slots for attaching a plurality of PCI adapter cards, and a logic device for providing separate bus signal pairs to each of the plurality of PCI adapter cards from a single signal pair of the PCI slot on the &mgr;ATX planar.

Abstract: A coded logical interrupt signal is sent between system or subsystem units in a data processing system. The logical interrupt is sent by a sending unit, that requests the interrupt, and is sent to a receiving unit that the sending unit wishes to interrupt. These coded logical interrupts are accumulated in the receiving unit. When the receiving unit is actually physically interrupted by control of the processor in the unit, all logical interrupts that have been accumulated are processed. The logical interrupt may be coded to indicate sending unit, that is the source of the interrupt, and the action being requested by the sending unit. If the interrupt includes only source information, the action information is sent separately by the sending unit to memory in the receiving unit. If the interrupt includes both source identification and action information, the receiving unit can interpret source and action directly from the interrupt.

Abstract: This disclosure relates to personal computer systems, and more particularly to a personal computer which provides for interrupt redirection of the activity of a microprocessor. The personal computer system has a multichannel bus for transferring data, a microprocessor for manipulating data and coupled to the bus, and a plurality of input/output devices coupled to the bus for receiving and delivering data for manipulation by the microprocessor. Each input/output device is capable of generating a logical interrupt signal indicative of a request for access to the microprocessor and of being remotely reset to a non-interrupt condition, and all of the devices deliver their logical interrupt signals through a common physical channel of the bus.

Abstract: A computing system including a host processor and at least one intelligent subsystem having attached devices, has two interrupt ports. The one intelligent subsystem and the attached devices are each viewed as a logical device by the host processor, and each is assigned a device identification number. The host processor provides direct and indirect commands to the logical devices. For direct commands, first physical interrupts are provided to the host processor serially from the logical devices through an Interrupt Status Port. For indirect commands, logical interrupts are stored in predetermined bit positions in a Device Interrupt Indentifier Port (DIIP) in accordance with the device identification numbers. A second single physical interrupt is provided to the host processor as long as there is at least one logical interrupt pending from at least one logical device as the result of an indirect command.

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

Abstract: A command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.