Patents by Inventor Ernest S. Cohen
Ernest S. Cohen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11726954Abstract: Aspects related to a resource-constrained system are described herein that can provide object storage services after a service interruption is resolved, even if all of the transactions that were pending and incomplete prior to the service interruption have not yet been recovered and/or executed. For example, file systems implemented by computing systems of the resource-constrained system may treat each file or directory as a separate object. Thus, a transaction directed to one file may not affect the file's directory or other files in the directory. As a result, the resource-constrained system can achieve read-after-write consistency without first recovering and executing the pending, incomplete transactions. Instead, read-after-write consistency for an object can be achieved simply by completing any pending, incomplete transaction directed to that object.Type: GrantFiled: September 29, 2020Date of Patent: August 15, 2023Inventors: Vandana Rungta, Michael F Brown, Ernest S Cohen, Srinivasa Rao Vempati, Arkady Michael Degtiarov, Benjamin Scott Dow
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Patent number: 11640240Abstract: Systems and methods are provided for managing the order of data written to a transaction log in a distributed storage system. In a system with multiple nodes, if sequencers are naively generated without taking into consideration inconsistencies among the different nodes generating the sequencers, then the sequencers may not increase for each data transaction. To alleviate this problem, the node committing the transaction to the transaction log may perform a consistent read and verifies that the sequencer advances. If the sequencer does not advance, the node can perform a context-dependent operation such as adjusting the sequencer, acknowledging the write without committing it to the transaction log, or rejecting the write altogether.Type: GrantFiled: September 30, 2021Date of Patent: May 2, 2023Assignee: Amazon Technologies, Inc.Inventors: Vishwas Narendra, John Pender, James Zuber, RaghuKishore Balivada, Mehak Mehta, Harishkumar Katagal, Preetham Kowshik, Addison Joseph Burns, Sameer Choudhary, Ernest S. Cohen, Abhishek Kannan, Arvinth Ravi, Nikhil Shah
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Patent number: 9104594Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.Type: GrantFiled: December 23, 2013Date of Patent: August 11, 2015Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
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Publication number: 20140122830Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.Type: ApplicationFiled: December 23, 2013Publication date: May 1, 2014Applicant: Microsoft CorporationInventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 8694712Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.Type: GrantFiled: December 5, 2006Date of Patent: April 8, 2014Assignee: Microsoft CorporationInventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 8615643Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.Type: GrantFiled: December 5, 2006Date of Patent: December 24, 2013Assignee: Microsoft CorporationInventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 8458522Abstract: Model-based testing is performed by repeatedly constructing a test strategy in which each test stimulus will lead to increased test coverage regardless of the nondeterministic choices made by the system under test, and following said strategy until coverage is increased. As soon as no such strategy exists, testing stops.Type: GrantFiled: October 6, 2010Date of Patent: June 4, 2013Assignee: Microsoft CorporationInventor: Ernest S. Cohen
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Publication number: 20120137275Abstract: This invention provides a technique for tracking information flow in a computer program or system, dynamically marking variables as high or low to indicate whether there has possibly been direct flow to that variable from the data initially marked high. Each conditional and loop test is classified as high or low, based only on low data. An assignment of an expression to a variable marks the variable high if the expression contains a variable marked high, or if the assignment occurs during execution of the body of a test that was classified as high; otherwise the assignment marks the variable low. Program execution aborts if the classifying expression for a test depends on the value of a high variable, or if the test is classified low, the test includes a high variable, and the test evaluates to false.Type: ApplicationFiled: November 28, 2010Publication date: May 31, 2012Applicant: Microsoft CorporationInventor: Ernest S. Cohen
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Publication number: 20120089869Abstract: Model-based testing is performed by repeatedly constructing a test strategy in which each test stimulus will lead to increased test coverage regardless of the nondeterministic choices made by the system under test, and following said strategy until coverage is increased. As soon as no such strategy exists, testing stops.Type: ApplicationFiled: October 6, 2010Publication date: April 12, 2012Applicant: Microsoft CorporationInventor: Ernest S. Cohen
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Patent number: 7788464Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.Type: GrantFiled: December 22, 2006Date of Patent: August 31, 2010Assignee: Microsoft CorporationInventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
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Patent number: 7644396Abstract: A method of replaying a recorded sequence of execution steps of a computer program or system to a selected target step while taking a minimal number of execution breaks includes calculating, for each of the steps, a predecessor step that can be reached in a minimal number of execution breaks. The total calculation time for the entire execution is linear in the number of steps, and allows subsequent calculation of an optimal path to any selected step to be obtained in time linear in the length of the optimal path.Type: GrantFiled: November 29, 2005Date of Patent: January 5, 2010Assignee: Microsoft CorporationInventor: Ernest S. Cohen
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Patent number: 7484073Abstract: Tagged translation lookaside buffer consistency is enabled in the presence of a hypervisor of a virtual machine computing environment, in which multiple processes of multiple logical processors of guests are hosted by a virtual machine monitor or hypervisor component. The virtual machine monitor or hypervisor component maintains tagged TLB data associated with the plurality of processes on behalf of each of the plurality of logical processors, thereby ensuring consistency of the tagged TLB data across all of the plurality of processes.Type: GrantFiled: July 12, 2006Date of Patent: January 27, 2009Assignee: Microsoft CorporationInventors: Ernest S. Cohen, Matthew D. Hendel
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Publication number: 20080155168Abstract: Various operations are provided that improve the scalability of virtual TLBs in multi-processor virtual machines, and they include: implicitly locking SPTs using per-processor generation counters; waiting for pending fills on other virtual processors to complete before servicing a GVA invalidation using the counters; write-protecting or unmaping guest pages in a deferred two-stage process or reclaiming SPTs in a deferred two-stage process; periodically coalescing two SPTs that shadow the same GPT with the same attributes; sharing SPTs between two SASes only at a specified level in a SPTT; flushing the entire virtual TLB using a generation counter; allocating a SPT to GPT from a NUMA node on which the GPT resides; having an instance for each NUMA node on which a virtual machine runs; and, correctly handling the serializing instructions executed by a guest in a virtual machine with more than one virtual processor sharing the virtual TLB.Type: ApplicationFiled: December 22, 2006Publication date: June 26, 2008Applicant: Microsoft CorporationInventors: John Te-Jui Sheu, Ernest S. Cohen, Matthew D. Hendel, Landy Wang, Rene Antonio Vega, Sharvil A. Nanavati
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Publication number: 20080133875Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Applicant: Microsoft CorporationInventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
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Publication number: 20080134174Abstract: Various operations are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, operations are disclosed that allow for determination of whether present entries in shadow page tables (SPTs) are stale by comparing shadowed guest page table (GPT) entries against snapshots taken when the entries were cached. Other operations are disclosed that allow a virtual machine monitor (VMM) to access shadow page table trees (SPTTs) by walking trees in software or in hardware. Still other operations are disclosed allowing the VMM to use a hash table to relate GVA ranges to SPTs that map them, thus significantly reducing the cost of having to walk each SPTT in order to invalidate desired GVA(s). And, finally, operations are disclosed allowing the VMM to determine global GVA ranges by checking a bitmap, when invalidating global GVAs.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Applicant: Microsoft CorporationInventors: John Te-Jui Sheu, Matthew D. Hendel, Landy Wang, Ernest S. Cohen, Rene Antonio Vega, Sharvil A. Nanavati
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Publication number: 20080016315Abstract: Tagged translation lookaside buffer consistency is enabled in the presence of a hypervisor of a virtual machine computing environment, in which multiple processes of multiple logical processors of guests are hosted by a virtual machine monitor or hypervisor component. The virtual machine monitor or hypervisor component maintains tagged TLB data associated with the plurality of processes on behalf of each of the plurality of logical processors, thereby ensuring consistency of the tagged TLB data across all of the plurality of processes.Type: ApplicationFiled: July 12, 2006Publication date: January 17, 2008Applicant: Microsoft CorporationInventors: Ernest S. Cohen, Matthew D. Hendel
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Patent number: 7310721Abstract: In a computer system that employs virtual memory, multiple versions of a given page are stored: a directory version, a table version, and a data version. The data version contains the data that a software object believes to be stored in the page. The directory and table versions of the page contains versions of the page's contents that have been modified in some manner to comply with a restriction on the address translation map employed by the virtual address system. When a page is being used by the virtual address system as a directory or table, then the directory or table versions, respectively, of that page are used. When a page is the target of a read request, the data version of the page is used.Type: GrantFiled: October 30, 2003Date of Patent: December 18, 2007Assignee: Microsoft CorporationInventor: Ernest S Cohen
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Patent number: 7287124Abstract: Address translation control (ATC) limits the mappings between virtual and physical addresses in order to implement a memory access policy. Each processor in a multi-processor system maintains a translation lookaside buffer (TLB) that caches mappings to speed translation of virtual addresses. Each processor also maintains a counter. Each time a processor's TLB is flushed, the processor's counter is incremented. When a link to a page is removed from an address translation map, the counter values for all of the processors are recorded. When that page is accessed by a processor, the recorded counter values are compared with the processor's current counter value to determine whether the processor's TLB has been flushed since the link to the page was removed from the map. An expensive TLB flush operation is delayed until needed, but still occurs early enough to prevent an invalid TLB entry from being used to violate the access policy.Type: GrantFiled: February 3, 2006Date of Patent: October 23, 2007Assignee: Microsoft CorporationInventor: Ernest S. Cohen
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Patent number: 7069389Abstract: Address translation control (ATC) limits the mappings between virtual and physical addresses in order to implement a memory access policy. Each processor in a multi-processor system maintains a translation lookaside buffer (TLB) that caches mappings to speed translation of virtual addresses. Each processor also maintains a counter. Each time a processor's TLB is flushed, the processor's counter is incremented. When a link to a page is removed from an address translation map, the counter values for all of the processors are recorded. When that page is accessed by a processor, the recorded counter values are compared with the processor's current counter value to determine whether the processor's TLB has been flushed since the link to the page was removed from the map. An expensive TLB flush operation is delayed until needed, but still occurs early enough to prevent an invalid TLB entry from being used to violate the access policy.Type: GrantFiled: November 26, 2003Date of Patent: June 27, 2006Assignee: Microsoft CorporationInventor: Ernest S. Cohen