Abstract: A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Abstract: A configurable circuit including a heterogeneous mix of processing elements is programmed.

Abstract: A reconfigurable partial response encoder manages the emitted spectrum of a digital signal.

Abstract: An apparatus and a system, as well as a method and article, may operate to shift a center frequency of selected ones of a plurality of received signals by selected amounts to provide a plurality of shifted signals located in a frequency domain, which may then be combined into a composite signal centered at a selected frequency.

Abstract: An apparatus and a system, as well as a method and article, may operate to search for a benefit associated with switching from receiving first information from a first network to receiving second information from a second network, and downloading a demodulation code to demodulate the second information received from the second network.

Abstract: Briefly, in accordance with one embodiment of the invention, an orthogonal frequency division multiplexing system may provide a dynamically calculated cyclic extension, the length of which may be based at least in part on a delay spread due to an experienced environmental condition. The length of the cyclic extension may be calculated by determining a channel impulse response, and then computing the energy distribution of the channel impulse response. The length of the cyclic extension may then be set according to the energy distribution of the channel impulse response.

Abstract: A QAM demodulator that samples an IF input modulated with data at a fractional complex sampling rate between one and two times the data rate. The use of a fractional sampling rate significantly reduces the number of components necessary to implement the demodulator, particularly in the equalizer section of the demodulator which corrects for channel distortion. The fractional sampling rate demodulator architecture of the invention provides a significant reduction in integrated circuit surface area needed in a VLSI implementation.