Abstract: An apparatus including a substrate, a power conversion circuit coupled to the substrate, a power prong coupled to the power conversion circuit, a device connector to couple to a device, and a device connector cable to couple the device connector to the power conversion circuit is disclosed.

Abstract: An apparatus including a substrate, a power conversion circuit coupled to the substrate, a power prong coupled to the power conversion circuit, a device connector to couple to a device, and a device connector cable to couple the device connector to the power conversion circuit is disclosed.

Abstract: The subject invention reveals a method to sample the drain source voltage of a power mosfet synchronous rectifier during its on time using high speed low voltage analog comparators and operational amplifiers. The method relies on a sampling switch such as a small signal level high voltage enhancement mode mosfet that is enabled when the drain source voltage of the power mosfet is near zero volts. The sampling switch isolates and protects the high speed low voltage analog circuit from the high voltages present on the drain of the power mosfet during the off state of the power mosfet.

Abstract: A composite high voltage schottky rectifier is revealed that provides a forward voltage slightly larger than a low voltage schottky rectifier combined with a high voltage breakdown capability. The composite rectifier can be formed from the combination of a low voltage schottky rectifier, a high voltage mosfet, and a few small passive components. A quarter bridge primary switching network similar in some ways to a half bridge primary switching network is revealed. The quarter bridge network consists of four switches with voltage stress equal to half the line voltage and the network applies one quarter of the line voltage to a primary magnetic circuit element network thereby reducing the number of primary winding turns required to one quarter by comparison to a common full bridge network. A synchronously switched buck post regulator is revealed for multi-output forward converters.

Abstract: Several novel gate drive circuits are revealed that accomplish optimal gate drive timing for zero voltage switches, both for the case in which there is sufficient drive energy to complete a turn on transition to zero volts and for the case for which there is insufficient drive energy available to complete a zero voltage turn on transition. Other related circuits are revealed which provide clamping to eliminate ringing and overshoot for secondary side placed ZVS drive chokes using a novel circuit and a winding of the ZVS drive choke used for gate drive for a synchronous rectifier. A boot strap gate drive energy circuit is revealed that provides gate drive energy for high side switches with reference terminals that swing both above and below ground. Gate drive circuits that rely on timing information from an auxiliary choke used for ZVS drive energy are also revealed.