Abstract: A switch interface connected between a fiber optic cable and a switching fabric includes a line interface block, a fabric interface block, and ingress and egress data transfer blocks coupled independently between the line interface and fabric interface blocks. The ingress data transfer block has a cross-connection block connected to the line interface block, four memories, two processors, and the fabric interface block. With use of the cross-connection block, at any one time, one memory is coupled to the line interface block, one memory is coupled to one processor, one memory is coupled to the other processor, and the last memory is coupled to the fabric interface. Controlled by a memory control, the memories rotate which block each is coupled to, so that each memory is coupled to every block within a single cycle. Therefore, data information units traversing the ingress data transfer block do not require to be transferred between memories during the processing stages.

Abstract: A telecommunications switch has a matrix architecture of n.times.m bus-interconnected, or space-switch interconnected, switch nodes together with additional switch nodes and n.times.m switch peripherals connected to the switch nodes externally of the bus (space-switch) interconnected switch node matrix. Fault protection redundancy is provided by providing each one of the peripherals with connections to two different switch nodes only one of which is enabled at any one time.

Abstract: A system for displaying graphic information such as a facial representation on a communications terminal. The facial representation is digitized, compressed and stored in memory at the appropriate control center of a communications network. Upon receipt of a display command the digitized data is retrieved from memory and transmitted to the called party's display terminal using modem technology.

Abstract: A digital circuit for the level measurement of PCM signals representing an analogue signal and encoded in accordance with a predetermined companding law comprising a selector circuit having position 0-n for selecting integers between 0 - n; a sampling circuit for successively sampling the input PCM signal 2.sup.n times, n being determined by the selector circuit; a connector circuit for converting each of the samples to its normalized power representation and for computing the average power of the samples; and means for determining the signal level equivalent of said average power in a conventional representation of power levels.

Abstract: A universal receiver/sender is achieved by providing circuitry having parameters setable by binary data words from the data processing unit of a switching facility. A clock signal generator provides output signals corresponding to respective binary instruction words whereas the parameters of an analogue signals receiving circuit are controlled by binary control words. A plurality of commutating filter circuits receive pass band limited analogue signals from the receiving circuit and under control of signals from the clock generator provide binary output signals indicative that a signal within a predetermined pass band has been received. Also provided is a data store for storing the required instruction and control words as well as the output signals from the filter circuits.

Abstract: An interface circuit adapted to selectively input serial and parallel PCM coded words and to selectively output serial and parallel PCM coded words is connected to a memory means. The memory means has a storage capacity for at least 2.sup.n memory words, each one having an address corresponding to a respective one of the PCM coded words appearing at the interface circuit and each one representing X db of signal level variation relative to its corresponding coded word. The output of the memory means is connected back to the parallel input of the interface circuit. A control means provides timing and control signals for loading the interface circuit with one of the coded words and for causing the memory means to be addressed at the location defined by the coded word. The control means includes means for circulating the coded word through the memory means a predetermined number of times M.