Abstract: Described is an arrangement for registering light, comprising: a MOS-transistor structure having a first source/drain region, a second source/drain region, and a bulk region at least partially between the first source/drain region and the second source/drain region, wherein the bulk region has a doping type different from another doping type of the first and the second source/drain regions, wherein in the bulk region charge carriers are generated in dependence of light impinging on the bulk region, wherein the generated charge carriers control a current flowing from the first source/drain region to the second source/drain region via at least a portion of the bulk region.

Abstract: Described is an arrangement for registering light, comprising: a MOS-transistor structure (101, 201, 401, 501, 601, 701) having a first source/drain region (103), a second source/drain region (105), and a bulk region (107) at least partially between the first source/drain region and the second source/drain region, wherein the bulk region has a doping type different from another doping type of the first and the second source/drain regions, wherein in the bulk region (107) charge carriers are generated in dependence of light (111) impinging on the bulk region (107), wherein the generated charge carriers control a current flowing from the first source/drain region (103) to the second source/drain region (105) via at least a portion of the bulk region.

Abstract: To provide a security-sensitive semiconductor product, particularly a smartcard chip, in which are produced not only electrically active structures (2, 3, 4, 5, 6) envisaged by the chip design in the form of circuit functions in and on a wafer (1), which may for example be composed of silicon, but also additional, electrically conductive parts (42, 61, 62) (tiles) of the filling structure, which are insulated from one another, are generated by means of a design program in the remaining residual areas, which greatly impedes, to the reverse engineer the analysis of the security-sensitive circuit structure situated beneath them. The contacts between the parts which are generated, which contacts are for interlinking the latter with the chance signal paths described, may be set “by hand” or by a combination of the design programs in question and a corresponding routing program.

Abstract: To provide a security-sensitive semiconductor product, particularly a smartcard chip, in which are produced not only electrically active structures (2, 3, 4, 5, 6) envisaged by the chip design in the form of circuit functions in and on a wafer (1), which may for example be composed of silicon, but also additional, electrically conductive parts (42, 61, 62) (tiles) of the filling structure, which are insulated from one another, are generated by means of a design program in the remaining residual areas, which greatly impedes, to the reverse engineer the analysis of the security-sensitive circuit structure situated beneath them. The contacts between the parts which are generated, which contacts are for interlinking the latter with the chance signal paths described, may be set “by hand” or by a combination of the design programs in question and a corresponding routing program.

Abstract: The invention relates to a method of generating a random-number sequence, and to a random-number generator, particularly for a chip card or a smart card.

Abstract: To provide a digitally switchable current source, by means of which no dangerous current spikes are produced at the switching instants, two digitally controllable switching transistors (MNn1, MNn2) are arranged in series with at least two parallel-arranged transistors (MNn) which are controllable by means of an analog voltage, while one of the two switching transistors is switched with the relevant inverted control signal and each one of the two switching transistors (MNn1, MNn2) is arranged in the current circuit whose current is to be controlled by the current source.

Abstract: The invention relates to a circuit for the detection of short voltage glitches in a supply voltage Vsup (glitch detector). According to the circuit the two inputs (VN, VP) of a comparator (C) are connected to a voltage divider (R1, R2, R3). In case of a short voltage glitch the connection of the first input (VN) of the comparator (C) to the voltage divider is interrupted via a first transistor (N1), so that this input is fixed at the previous voltage level, while the other input (VP) changes in accordance with the voltage glitch. If the change is strong enough, there is a polarity reversal at the input of the comparator (C) and thus a flipping of the output signal (OUT) which shows the detection of a voltage glitch.

Abstract: To provide a digitally switchable current source, by means of which no dangerous current spikes are produced at the switching instants, two digitally controllable switching transistors (MNn1, MNn2) are arranged in series with at least two parallel-arranged transistors (MNn) which are controllable by means of an analog voltage, while one of the two switching transistors is switched with the relevant inverted control signal and each one of the two switching transistors (MNn1, MNn2) is arranged in the current circuit whose current is to be controlled by the current source.

Abstract: The invention relates to a circuit for the detection of short voltage glitches in a supply voltage Vsup (glitch detector). According to the circuit the two inputs (VN, VP) of a comparator (C) are connected to a voltage divider (R1, R2, R3). In case of a short voltage glitch the connection of the first input (VN) of the comparator (C) to the voltage divider is interrupted via a first transistor (N1), so that this input is fixed at the previous voltage level, while the other input (VP) changes in accordance with the voltage glitch. If the change is strong enough, there is a polarity reversal at the input of the comparator (C) and thus a flipping of the output signal (OUT) which shows the detection of a voltage glitch.

Abstract: To provide an electric or electronic circuit arrangement (100) and a method of protecting at least a chip arrangement (200), for example, at least a (semiconductor) chip arrangement, particularly at least a controller chip arrangement for a chip card or smart card from manipulation and/or abuse, in which an optical attack by means of light irradiation on a controller chip arrangement itself and on a dielectric coating, particularly an insulating layer and/or passivation layer and/or further protective coating covering the controller chip arrangement for protecting the integrated circuit from external influences, both on the front side of the controller chip arrangement and on the substantially unprotected rear side of the controller chip arrangement can be reliably and permanently averted,

Abstract: To provide an electric or electronic circuit arrangement (100), it is proposed that at least one signal-generating unit (40), particularly at least an oscillator unit is connected to the contact terminals (22, 27) of the integrated circuit, the output frequency (fmeas.) of which unit is substantially determined by the specific capacitance (C), the signal-generating unit (40) precedes at least a first counting unit (50) which is clocked at the output frequency (fmeas.

Abstract: The invention relates to a method of generating a random-number sequence, and to a random-number generator, particularly for a chip card or a smart card.