Abstract: A delay device includes storage elements arranged in at least two rows 4, 5; 6, 7 in an integrated circuit, preferably in switched-capacitor technology. The delay device 2; 3 has an even number of storage elements. A first clock signal is provided from which, for producing a delay time equal to an odd multiple of the clock period of the first clock signal, a second clock signal is derived by means of a clock generation circuit 9, this second clock signal clocking the storage elements and being derived from the first clock signal in such a manner that one clock pulse of the first clock signal is suppressed in a selectable or given cycle and all the other clock pulses in the cycle are taken over in the second clock signal.