Abstract: An arrangement comprises a memory device for storing data, and a program-controlled unit with a memory interface for reading data out of the memory device. The memory device is supplied with a first clock signal and transmits the data at the rate of a second clock signal, and the second clock signal to the memory interface when the memory interface performs a read access. The first clock signal is also supplied to the memory interface which generates from this signal a third clock signal which has the same frequency as the first and second clock signal but a predetermined phase shift with respect to the second clock signal. The memory interface accepts the data with the rising and/or falling edges of the third clock signal or the inverted third clock signal, and the third clock signal is also used as clock signal by other components of the memory interface.

Abstract: The document describes an arrangement having a first memory for storing data, switching devices which stipulate whether access to the first memory involves output of the data stored in the first memory or other data, and a second memory for storing the other data. The arrangement described is distinguished in that it contains a third memory (103, 203, 310), which is addressed by the address (A) which is used to access the first memory or by a portion (AH) of this address and contains information about which data in the first memory are to be replaced with other data.