Abstract: The invention relates to a MOS memory unit for serial information processing, in particular a shift register stage with an EEPROM cell having a floating gate transistor. According to the prior art, the gate electrodes of all floating gate transistors of a memory unit have the same potential. The result is that two programming cycles must be performed for complete programming, entailing a high current consumption. In accordance with the invention, the drain electrode of the floating gate transistor is connected via an inverter stage to its gate electrode. This halves the total programming time and hence also the total programming current in comparison with the prior art.

Abstract: The invention relates to a method and a circuit array for regulating the supply voltage of a load as may be found, for example, in the form of an integrated circuit in a chip card. An integrated circuit of this type contains a non-volatile memory and the control logic needed to read out the information stored in the non-volatile memory, but with the transmission of both energy and data being wireless, for example inductive. Data is transmitted by suitable modulation of the voltage supply. In order for the reader to clearly evaluate the read-out logic states, it is proposed in accordance with the invention that during output of the first logic level the supply voltage of the load is generated by serial regulation and that during output of the second logic level the terminal voltage of the voltage source is under parallel regulation.

Abstract: A current having a high negative temperature coefficient can be tapped from a current source circuit connected as a loop out of two current mirror circuits and having a resistor. Furthermore, a current source circuit of this type made with CMOS technology has a high current requirement. The invention permits a reduction of these drawbacks by replacing the resistor with a connected capacitor.

Abstract: The invention relates to a voltage multiplying circuit having several stages, with each stage having a pumping capacitor and several MOS switching transistors. The switching transistors are so controlled by clock signals that the charge of a pumping capacitor of one stage is transferred to the pumping capacitor of the following stage. Operation of a circuit of this type with operating voltages substantially lower than 5 V entails considerable drawbacks. In accordance with the invention, therefore, each stage of a voltage multiplying circuit of this type is fitted with an additional transistor and an additional correction capacitor. As a result, the circuit in accordance with the invention is suppliable with an operating voltage of 2 V, for example. In another circuit arrangement, the transistors of the last two or three stages of the voltage multiplying circuit are of one conductivity type, while the transistors of the previous stages are of the opposite conductivity type.

Abstract: A circuit arrangement includes a MOS field effect transistor as a variable resistance in series with a load such as an integrated circuit across a power supply with means for controlling the variable resistance to establish a very constant supply or input voltage to the load. A switch may be included to apply a constant supply or input voltage of different known values to a load such as an oscillator requiring different voltages at different stages of operation.