Abstract: Two capacitors are provided for demodulating an amplitude-modulated signal and can be supplied with a signal that is rectified by a diode and that is at a voltage. The half-cycles of this signal are used for alternately charging the first or second capacitor using a switch. The capacitors are discharged using switches. Comparing the amplitude values, which are stored in the capacitors, of successive half-cycles in an evaluation unit allows simple and precise demodulation, which can be achieved with few components and can be carried out at very high frequencies.

Abstract: The invention provides a circuit configuration for demodulating a voltage that is ASK modulated by altering the amplitude between a low level and a high level. In this case, a first and a second charging circuit each produce a charging voltage and decoupling device decouples the first charging circuit when there is a prescribed ratio between the charging voltage of the second charging circuit and an input voltage for the rectifier circuit.

Abstract: The invention provides a circuit configuration for demodulating a voltage that is ASK modulated by altering the amplitude between a low level and a high level. In this case, a first and a second charging circuit each produce a charging voltage and a decoupling device decouples the first charging circuit when there is a prescribed ratio between the charging voltage of the second charging circuit and an input voltage for the rectifier circuit.

Abstract: Two capacitors are provided for demodulating an amplitude-modulated signal and can be supplied with a signal that is rectified by a diode and that is at a voltage. The half-cycles of this signal are used for alternately charging the first or second capacitor using a switch. The capacitors are discharged using switches. Comparing the amplitude values, which are stored in the capacitors, of successive half-cycles in an evaluation unit allows simple and precise demodulation, which can be achieved with few components and can be carried out at very high frequencies.

Abstract: An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

Abstract: A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.

Abstract: The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.

Abstract: An integrated memory contains two normal read amplifiers and two first redundant read amplifiers. It also contains bit lines which are combined into at least two individually addressable normal columns, at least one of which from each normal column is connected to one of the normal read amplifiers. It also has first redundant bit lines which are combined into one individually addressable redundant column, at least one of which is connected to one of the redundant read amplifiers. The first redundant read amplifier and its redundant columns are provided for replacing the two normal read amplifiers and one of the normal columns.

Abstract: A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.

Abstract: The decoder element is used for producing an output signal having three different potentials at an output. The second potential is situated between the first potential and the third potential. The decoder element makes it possible to produce any one of the three potentials at its output based upon the potentials on its connections.