Patents by Inventor Ernst Stahl
Ernst Stahl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090051418Abstract: An integrated circuit device and a method for providing distributed voltage regulation. The device includes a plurality of memory cell arrays and access circuitry dependent on one or more regulated voltages generated on the device and a plurality of pulsed digital distributed output units configured to generate the one or more regulated voltages. The device also includes a voltage regulator control logic configured to generate one or more control signals to control the distributed output units based, at least in part, on a comparison between one or more reference voltages and the one or more regulated voltages.Type: ApplicationFiled: August 21, 2007Publication date: February 26, 2009Inventors: DIETMAR GOGL, Ernst Stahl
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Publication number: 20090040857Abstract: An integrated circuit includes a decoupling capacitor configured to be enabled in response to the decoupling capacitor not increasing a standby current of the integrated circuit and disabled in response to the decoupling capacitor increasing the standby current of the integrated circuit.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Inventors: Grant McNeil, Ernst Stahl
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Patent number: 7339841Abstract: A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.Type: GrantFiled: September 16, 2005Date of Patent: March 4, 2008Assignee: Infineon Technologies AGInventors: Martin Versen, Klaus Nierle, Oliver Kiehl, Ernst Stahl
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Publication number: 20070081366Abstract: A system includes a charge pump configured to provide a boosted voltage, a voltage source configured to provide a voltage less than the boosted voltage, and a load. The system includes a coupling capacitance coupled to the load, a first switch coupled between the charge pump and the load, and a second switch coupled between the voltage source and the load.Type: ApplicationFiled: October 11, 2005Publication date: April 12, 2007Inventor: Ernst Stahl
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Publication number: 20070064505Abstract: A method of testing internal signals of a memory for timing marginalities which may result in unstable operation includes: delaying internal address signals of the memory by an amount great enough so that data cannot be validly written to and read from memory locations which are accessed by address signals having timing marginalities which are delayed but small enough so that data can be validly written to and read from memory locations which are accessed by address signals not having such timing marginalities which are delayed. Data is then written to and read from memory locations which are accessed by delayed address signals, and a determination is made as to whether the data read from any memory location does not correspond with the data written to such memory location.Type: ApplicationFiled: September 16, 2005Publication date: March 22, 2007Inventors: Martin Versen, Klaus Nierle, Oliver Kiehl, Ernst Stahl
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Patent number: 7187599Abstract: An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to delay a signal a first delay. The second delay circuit has a second delay circuit topology configured to provide a second delay in a circuit loop that is configured to be monitored and provide an oscillating signal. The second delay circuit topology is substantially the same as the first delay circuit topology and the first delay circuit is configured to be trimmed to adjust the first delay based on the second delay and the oscillating signal.Type: GrantFiled: May 25, 2005Date of Patent: March 6, 2007Assignee: Infineon Technologies North America Corp.Inventors: Josef Schnell, Ernst Stahl
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Publication number: 20060268632Abstract: An integrated circuit chip including a first delay circuit and a second delay circuit. The first delay circuit has a first delay circuit topology configured to delay a signal a first delay. The second delay circuit has a second delay circuit topology configured to provide a second delay in a circuit loop that is configured to be monitored and provide an oscillating signal. The second delay circuit topology is substantially the same as the first delay circuit topology and the first delay circuit is configured to be trimmed to adjust the first delay based on the second delay and the oscillating signal.Type: ApplicationFiled: May 25, 2005Publication date: November 30, 2006Inventors: Josef Schnell, Ernst Stahl
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Publication number: 20060232326Abstract: A reference circuit that includes a first circuit configured to provide a temperature dependent current, a second circuit configured to provide a first current, and a third circuit. The third circuit is configured to provide a temperature dependent voltage based on the first current and the temperature dependent current. The temperature dependent voltage has a voltage versus temperature slope established by the third circuit and a voltage level established by the first current.Type: ApplicationFiled: April 18, 2005Publication date: October 19, 2006Inventors: Helmut Seitz, Russell Houghton, Ernst Stahl
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Patent number: 7060529Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.Type: GrantFiled: May 7, 2004Date of Patent: June 13, 2006Assignee: Infineon Technologies AGInventors: Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller, Ernst Stahl, Hartmud Terletzki, Thomas Vogelsang
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Publication number: 20050001298Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.Type: ApplicationFiled: May 7, 2004Publication date: January 6, 2005Inventors: Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller, Ernst Stahl, Hartmud Terletzki, Thomas Vogelsang
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Patent number: 6815803Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.Type: GrantFiled: June 16, 2000Date of Patent: November 9, 2004Assignee: Infineon Technologies AGInventors: Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller, Ernst Stahl, Hartmud Terletzki, Thomas Vogelsang
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Patent number: 6760248Abstract: A memory device and method of manufacturing thereof having a voltage regulator with distributed output transistor. A novel approach for the bitline high voltage (VBLH) generation is used to save chip area by allowing narrower power bussing. The output transistor is distributed along the array edge. In addition, the transistor is divided into sections with different channel widths to compensate for current drive losses due to voltage drops along the VDD power bus. The IR-drop on the VBLH line is eliminated, and a constant output voltage is provided along the array edge.Type: GrantFiled: October 9, 2002Date of Patent: July 6, 2004Assignee: Infineon Technologies AGInventor: Ernst Stahl
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Patent number: 6730989Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.Type: GrantFiled: June 16, 2000Date of Patent: May 4, 2004Assignee: Infineon Technologies AGInventors: Manfred Reithinger, Mike Killian, Gerd Frankowsky, Oliver Kiehl, Gerhard Mueller, Ernst Stahl, Hartmud Terletzki, Thomas Vogelsang
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Publication number: 20040076034Abstract: A memory device and method of manufacturing thereof having a voltage regulator with distributed output transistors. A novel approach for the bitline high voltage (VBLH) generation is used to save chip area by allowing narrower power bussing. The output transistor is distributed along the array edge. In addition, the transistor is divided into sections with different channel widths to compensate for current drive losses due to voltage drops along the VDD power bus. The IR-drop on the VBLH line is eliminated, and a constant output voltage is provided along the array edge.Type: ApplicationFiled: October 9, 2002Publication date: April 22, 2004Inventor: Ernst Stahl