Patents by Inventor Ernst W. Mayer

Ernst W. Mayer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tiered schematic-driven layout synchronization in electronic design automation
    Patent number: 8762912
    Abstract: Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: June 24, 2014
    Assignee: Synopsys, Inc.
    Inventors: Wern-Jieh Sun, Haichun Chun, Ernst W. Mayer, Greg Woolhiser, Kuldeep Karlcut
  • TIERED SCHEMATIC-DRIVEN LAYOUT SYNCHRONIZATION IN ELECTRONIC DESIGN AUTOMATION
    Publication number: 20110107281
    Abstract: Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 5, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: Wern-Jieh Sun, Haichun Chun, Ernst W. Mayer, Greg Woolhiser, Kuldeep Karlcut