Patents by Inventor Errol T. Ryan
Errol T. Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9435947Abstract: Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor.Type: GrantFiled: September 10, 2015Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES INC.Inventor: Errol T. Ryan
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Publication number: 20150378096Abstract: Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor.Type: ApplicationFiled: September 10, 2015Publication date: December 31, 2015Inventor: Errol T. RYAN
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Patent number: 9209075Abstract: Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor.Type: GrantFiled: June 25, 2013Date of Patent: December 8, 2015Assignee: GLOBALFOUNDRIES INC.Inventor: Errol T Ryan
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Patent number: 8946082Abstract: Embodiments of methods for forming a semiconductor device are provided. The method includes forming a metal layer overlying a dielectric material. A thickness of the metal layer is reduced including oxidizing an exposed outer portion of the metal layer to form a metal oxide portion overlying a remaining portion of the metal layer and removing the metal oxide portion.Type: GrantFiled: September 16, 2011Date of Patent: February 3, 2015Assignee: Globalfoundries, Inc.Inventor: Errol T. Ryan
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Publication number: 20140374915Abstract: Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor.Type: ApplicationFiled: June 25, 2013Publication date: December 25, 2014Inventor: Errol T. RYAN
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Patent number: 8871635Abstract: Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.Type: GrantFiled: May 8, 2012Date of Patent: October 28, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Chanro Park, Errol T. Ryan
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Publication number: 20140145332Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a graphene liner layer in at least the trench/via, forming a copper-based seed layer on the graphene liner layer, depositing a bulk copper-based material on the copper-based seed layer so as to overfill the trench/via, and performing at least one chemical mechanical polishing process to remove at least excess amounts of the bulk copper-based material and the copper-based seed layer positioned outside of the trench/via to thereby define a copper-based conductive structure with a graphene liner layer positioned between the copper-based conductive structure and the layer of insulating material.Type: ApplicationFiled: November 26, 2012Publication date: May 29, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Errol T. Ryan, Zoran Krivokapic, Xunyuan Zhang, Christian Witt, Ming He, Larry Zhao
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Patent number: 8704372Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.Type: GrantFiled: March 22, 2013Date of Patent: April 22, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Errol T. Ryan, Xunyuan Zhang
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Patent number: 8691696Abstract: Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.Type: GrantFiled: May 21, 2012Date of Patent: April 8, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Xiuyu Cai, Xunyuan Zhang, Ruilong Xie, Errol T. Ryan, John Iacoponi
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Publication number: 20130309868Abstract: Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.Type: ApplicationFiled: May 21, 2012Publication date: November 21, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Xiuyu Cai, Xunyuan Zhang, Ruilong Xie, Errol T. Ryan, John A. Iacoponi
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Publication number: 20130299994Abstract: Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.Type: ApplicationFiled: May 8, 2012Publication date: November 14, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Chanro Park, Errol T. Ryan
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Publication number: 20130241062Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.Type: ApplicationFiled: March 22, 2013Publication date: September 19, 2013Applicant: Globalfoundries IncInventors: Errol T. Ryan, Xunyuan Zhang
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Publication number: 20130221524Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes an interlayer dielectric material having a top surface and overlying semiconductor devices formed on a semiconductor substrate. The integrated circuit includes a metal interconnect formed in the interlayer dielectric material. The metal interconnect includes an upper surface to which an insulating monolayer is bonded. The integrated circuit further includes a dielectric cap that overlies the top surface of the interlayer dielectric material and encapsulates the insulating monolayer.Type: ApplicationFiled: February 29, 2012Publication date: August 29, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Roderick A. Augur, Errol T. Ryan
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Publication number: 20130175680Abstract: A multiphase ultra low k dielectric process is described incorporating a first precursor comprising at least one of carbosilane and alkoxycarbosilane molecules containing the group Si—(CH2)n—Si where n is an integer 1, 2 or 3 and a second precursor containing the group Si—R* where R* is an embedded organic porogen, a high frequency radio frequency power in a PECVD chamber and an energy post treatment including ultraviolet radiation. An ultra low k porous SiCOH dielectric material having at least one of a k in the range from 2.2 to 2.3, 2.3 to 2.4, 2.4 to 2.5, and 2.5 to 2.55 and a modulus of elasticity greater than 5, 6, 7.8 and 9 GPa, respectively and a semiconductor integrated circuit comprising interconnect wiring having porous SiCOH dielectric material as described above.Type: ApplicationFiled: January 10, 2012Publication date: July 11, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen M. Gates, Alfred Grill, Errol T. Ryan
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Patent number: 8431482Abstract: Integrated circuits, a process for recessing an embedded copper feature within a substrate, and a process for recessing an embedded copper interconnect within an interlayer dielectric substrate of an integrated circuit are provided. In an embodiment, a process for recessing an embedded copper feature, such as an embedded copper interconnect, within a substrate, such as an interlayer dielectric substrate, includes providing a substrate having an embedded copper feature disposed therein. The embedded copper feature has an exposed surface and the substrate has a substrate surface adjacent to the exposed surface of the embedded copper feature. The exposed surface of the embedded copper feature is nitrided to form a layer of copper nitride in the embedded copper feature. Copper nitride is selectively etched from the embedded copper feature to recess the embedded copper feature within the substrate.Type: GrantFiled: January 31, 2012Date of Patent: April 30, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventors: Errol T. Ryan, Xunyuan Zhang
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Publication number: 20130072019Abstract: Embodiments of methods for forming a semiconductor device are provided. The method includes forming a metal layer overlying a dielectric material. A thickness of the metal layer is reduced including oxidizing an exposed outer portion of the metal layer to form a metal oxide portion overlying a remaining portion of the metal layer and removing the metal oxide portion.Type: ApplicationFiled: September 16, 2011Publication date: March 21, 2013Applicant: GLOBALFOUNDRIES INC.Inventor: Errol T. Ryan
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Patent number: 8367562Abstract: Ultrathin layers are deposited by chemical vapor deposition (CVD) with reduced discontinuities, such as pinholes. Embodiments include depositing a material on a wafer by CVD while rotating the CVD showerhead and/or the wafer mounting surface, e.g., at least 45°. Embodiments include rotating the showerhead and/or mounting surface continuously through the deposition of the material. Embodiments also include forming subfilms of the material and rotating the showerhead and/or mounting surface after the deposition of each subfilm. The rotation of the showerhead and/or mounting surface averages out the non-uniformities introduced by the CVD showerhead, thereby eliminating discontinuities and improving within wafer and wafer-to-wafer uniformity.Type: GrantFiled: March 16, 2009Date of Patent: February 5, 2013Assignee: Globalfoundries Inc.Inventor: Errol T. Ryan
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Patent number: 8357609Abstract: Metal interconnects are formed with larger grain size and improved uniformity. Embodiments include patterning metal layers into metal interconnects and vias prior to depositing a dielectric layer. An embodiment includes forming metal layers on a substrate, patterning the metal layers to form metal interconnect lines and vias, and forming a dielectric layer on the substrate, metal interconnect lines, and vias, thereby filling gaps between the metal interconnect lines and between the vias. The metal layers may be annealed prior to patterning. A liner may be formed on the sidewalls of the metal interconnect lines and vias prior to forming the dielectric layer. The dielectric layer may be formed of a porous material with a dielectric constant less than 2.4.Type: GrantFiled: May 4, 2010Date of Patent: January 22, 2013Assignee: GLOBALFOUNDRIES Inc.Inventor: Errol T. Ryan
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Publication number: 20110275214Abstract: Metal interconnects are formed with larger grain size and improved uniformity. Embodiments include patterning metal layers into metal interconnects and vias prior to depositing a dielectric layer. An embodiment includes forming metal layers on a substrate, patterning the metal layers to form metal interconnect lines and vias, and forming a dielectric layer on the substrate, metal interconnect lines, and vias, thereby filling gaps between the metal interconnect lines and between the vias. The metal layers may be annealed prior to patterning. A liner may be formed on the sidewalls of the metal interconnect lines and vias prior to forming the dielectric layer. The dielectric layer may be formed of a porous material with a dielectric constant less than 2.4.Type: ApplicationFiled: May 4, 2010Publication date: November 10, 2011Applicant: GLOBALFOUNDRIES Inc.Inventor: Errol T. Ryan
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Publication number: 20100233879Abstract: Ultrathin layers are deposited by chemical vapor deposition (CVD) with reduced discontinuities, such as pinholes. Embodiments include depositing a material on a wafer by CVD while rotating the CVD showerhead and/or the wafer mounting surface, e.g., at least 45°. Embodiments include rotating the showerhead and/or mounting surface continuously through the deposition of the material. Embodiments also include forming subfilms of the material and rotating the showerhead and/or mounting surface after the deposition of each subfilm. The rotation of the showerhead and/or mounting surface averages out the non-uniformities introduced by the CVD showerhead, thereby eliminating discontinuities and improving within wafer and wafer-to-wafer uniformity.Type: ApplicationFiled: March 16, 2009Publication date: September 16, 2010Inventor: Errol T. Ryan