Abstract: A memory device comprising a memory cell comprising a storage element including a phase change memory; and a bilayer formed on a first side and a second side of the memory cell, the bilayer including an inner layer comprising a first nitride and an outer layer comprising a second nitride.

Abstract: Techniques for semiconductor devices including amorphous silicon are disclosed. In the illustrative embodiment, trenches are etched through several layers of a memory during manufacture, including through a phase-change layer. To protect the phase-change layer during further processing steps, amorphous silicon is applied to the phase-change layer using low-temperature chemical vapor deposition, which can be done without exceeding the melting point of the phase-change layer. The amorphous silicon can be oxidized, forming a protective silicon oxide layer around the phase-change layer.

Abstract: A semiconductor fabrication method, a semiconductor device and a semiconductor module. The method comprises: providing a stack on a substrate, the stack including a plurality of device layers comprising electrically conductive layers; patterning the stack using an etch to form trenches extending therethrough and pillars between the trenches; providing a carbon-containing liner on sidewalls of the trenches; wet cleaning and drying the stack after providing the carbon-containing liner; filling spaces between the pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form the semiconductor device. The carbon-containing liner may include a carbon-doped liner, such as a carbon-doped oxide liner provided by way of atomic layer deposition of an oxide at temperatures between about 100 degrees Celsius to about 300 degree Celsius using carbon as a precursor.

Abstract: A semiconductor fabrication method, a semiconductor device and a semiconductor module. The method comprises: providing a stack on a substrate, the stack including a plurality of device layers comprising electrically conductive layers; patterning the stack using an etch to form trenches extending therethrough and pillars between the trenches; providing an a-Si-containing liner on sidewalls of the pillars; filling spaces between the pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form the semiconductor device. The a-Si-containing liner may include a liner made substantially of amorphous silicon, or a liner including a non-uniform distribution of a-Si and silicon nitride.

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

Abstract: Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.

Abstract: Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to fully aligned via structures having relaxed gapfills and methods of manufacture. The method includes: selectively depositing a capping material on a conductive material within a plurality of interconnect structures to form capped interconnect structures; depositing at least one insulator material over the capped interconnect structures; forming a fully aligned via structure through the at least one insulator material to expose the capping material; filling the fully aligned via structure with an alternative metal; and depositing a metal material on the alternative metal in the fully aligned via structure.

Abstract: Interconnects and methods for forming interconnects. An interconnect opening is formed in a dielectric layer, and a conductive layer is formed in the interconnect opening. A modified section is formed in the conductive layer near a top surface of the conductive layer. After the modified section is formed, the modified section of the conductive layer is recessed with an etching process that at least partially removes the modified section. The modified section may have a composition that includes niobium.