Patents by Inventor Erwan Le Roy
Erwan Le Roy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7884024Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.Type: GrantFiled: May 29, 2007Date of Patent: February 8, 2011Assignee: DCG Systems, Inc.Inventors: Erwan Le Roy, Chun-Cheng Tsao, Theodore R. Lundquist, Rajesh Kumar Jain
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Patent number: 7697146Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, light is directed on the integrated circuit and based upon the detection of interference fringes, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. When the floor approaches the underlying circuit structures, some light is reflected from the floor of the trench and some light penetrates the substrate and is reflected off the underlying circuit structures. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Processing may be controlled as function of the detection of interference fringes.Type: GrantFiled: February 24, 2006Date of Patent: April 13, 2010Assignee: DCG Systems, Inc.Inventors: Erwan Le Roy, Chun-Cheng Tsao, Theodore R. Lundquist
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Patent number: 7488937Abstract: A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal of Ga at the trench floor using XeF2, as well as the deposition of an insulating layer onto the trench floor.Type: GrantFiled: October 17, 2005Date of Patent: February 10, 2009Assignee: Credence Systems CorpInventors: Erwan Le Roy, William B. Thompson
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Publication number: 20070293052Abstract: An apparatus and method for processing an integrated circuit employing optical interference fringes. During processing, one or more wavelength lights are directed on the integrated circuit and based upon the detection of interference fringes and characteristics of the same, further processing may be controlled. One implementation involves charged particle beam processing of an integrated circuit as function of detection and/or characteristics of interference fringes. A charged particle beam trench milling operation is performed in or on the substrate of an integrated circuit. Light is directed on the floor of the trench. Interference fringes may be formed from the constructive or destructive interference between the light reflected from the floor and the light from the circuit structures. Resulting fringes will be a function, in part, of the thickness and/or profile of the trench floor. Milling may be controlled as a function of the detected fringe patterns.Type: ApplicationFiled: May 29, 2007Publication date: December 20, 2007Applicant: Credence Systems CorporationInventors: Erwan Le Roy, Chun-Cheng Tsao, Theodore Lundquist, Rajesh Jain
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Publication number: 20070087572Abstract: A method for observing voltage contrast from buried structures in SOI. The method includes depositing a thin transparent metal layer over the BOx to dissipate charging of the oxide, and using a low FIB beam current to avoid damage due to ion implantation and direct ion beam damage.Type: ApplicationFiled: September 26, 2006Publication date: April 19, 2007Inventors: Erwan Le Roy, Mark Thompson, William Thompson
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Patent number: 7135123Abstract: The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.Type: GrantFiled: January 14, 2004Date of Patent: November 14, 2006Assignee: Credence Systems CorporationInventors: Mark Alan Thompson, Erwan Le Roy, Theodore Lundquist, William B. Thompson, Catherine Kardach
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Patent number: 7115426Abstract: A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to those regions which are thicker to correct observed non-uniformities in the trench floor thickness by varying the pixel dwell time across the milled area. The interference fringe mapping may be used to develop computerized contour lines to automate the pixel dwell time variations as described above, for correcting non-uniformities in the trench floor thickness. The method may be applied to applications other than trench formation for backside editing, such as monitoring progress in forming a milled object.Type: GrantFiled: January 7, 2005Date of Patent: October 3, 2006Assignee: Credence Systems CorporationInventors: Erwan Le Roy, Patricia Le Coupanec, Theodore R. Lundquist, William B. Thompson, Mark A. Thompson, Lokesh Johri
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Patent number: 7036109Abstract: Methods and apparatus for integrated circuit diagnosis, characterization or modification using a focused ion beam. A method for editing an integrated circuit includes acquiring an image of structures of an integrated circuit by applying a focused ion beam to an outer surface of the integrated circuit to visualize structures beneath the outer surface of the integrated circuit. The method includes using the image to find a location of a circuit element in the integrated circuit and then performing one or more editing operations on the circuit element by applying a focused ion beam to the location found.Type: GrantFiled: October 17, 2002Date of Patent: April 25, 2006Assignee: Credence Systems CorporationInventors: Chun-Cheng Tsao, Theodore R. Lundquist, William Thompson, Erwan Le Roy, Eugene A. Delenia
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Patent number: 6958248Abstract: A method and system for registering a CAD layout to a Focused Ion Beam image for through-the substrate probing, without using an optical image and without requiring biasing, includes an improved method of trench endpointing during the FIB milling operation with a low beam energy. The method further includes removal of Ga at the trench floor using XeF2, as well as the deposition of an insulating layer onto the trench floor.Type: GrantFiled: February 27, 2004Date of Patent: October 25, 2005Assignee: Credence Systems CorporationInventors: Erwan Le Roy, William B. Thompson
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Patent number: 6955930Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool.Type: GrantFiled: May 30, 2002Date of Patent: October 18, 2005Assignee: Credence Systems CorporationInventors: Erwan Le Roy, Chun-Cheng Tsao
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Method and apparatus for forming a cavity in a semiconductor substrate using a charged particle beam
Patent number: 6855622Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The floor of the trench is formed so as to be as smooth and planar as possible, thereby preventing undesirable exposure of the underlying active regions through any unknown or undesired cavity caused by scratches or pits or a deeper than desired sidewall.Type: GrantFiled: May 30, 2002Date of Patent: February 15, 2005Assignee: NPTest, LLCInventors: Erwan Le Roy, Mark A. Thompson -
Method and apparatus for determining thickness of a semiconductor substrate at the floor of a trench
Publication number: 20030224543Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The process includes a precise optical endpointing technique to monitor the remaining thickness of the semiconductor substrate at the floor of the trench. It is important to terminate etching of the trench so that the trench floor extends as close to the active semiconductor structures as desired and yet is not detrimental to device operation. This is done without introducing a need for any additional tool.Type: ApplicationFiled: May 30, 2002Publication date: December 4, 2003Applicant: Schlumberger Technologies, Inc.Inventors: Erwan Le Roy, Chun-Cheng Tsao -
Publication number: 20030224601Abstract: Apparatus and method for exposing a selected feature of an integrated circuit device such as a selected portion of the metallization layer, from the backside of the integrated circuit substrate without disturbing adjacent features of the device such as the active semiconductor regions. This is performed using an FIB (focused ion beam) etching process in conjunction with observation by an optical microscope to form a trench through the substrate. The floor of the trench is formed so as to be as smooth and planar as possible, thereby preventing undesirable exposure of the underlying active regions through any unknown or undesired cavity caused by scratches or pits or a deeper than desired sidewall.Type: ApplicationFiled: May 30, 2002Publication date: December 4, 2003Inventors: Erwan Le Roy, Mark A. Thompson