Abstract: An electronic component includes a substrate, an active stack formed above the substrate and including: a layer of p-type doped Gallium Nitride GaN, disposed above the substrate, and a layer of a semiconductor material disposed on the layer of p-type doped Gallium Nitride GaN; the component including two side zones located on either side of the layer of p-type doped GaN, the two side zones being oxygen-implanted.

Abstract: A high electron mobility transistor includes a stack of layers including a passivation layer and a heterojunction including a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at the interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer; a source metal contact and/or a drain metal contact and a gate electrode; an n+ doped zone situated inside the heterojunction; the source metal contact and/or the drain metal contact being positioned at the level of a recess formed in the stack of layers, the source metal contact and/or said drain metal contact having a thickness defined by an upper face and a lower face substantially parallel to the plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first and second semiconductor layers.

Abstract: The invention aims for a polarisation circuit of a power component comprising a capacitive dividing bridge and a resistive dividing bridge formed on the same substrate as the component. An additional electrode 1? in the front face 100 of the substrate makes it possible to adjust one of the capacitance values of the capacitive dividing bridge according to the other of the capacitance values coming from one of the electrodes of the power component. The sizing of this additional electrode furthermore makes it possible to obtain a leakage resistance contributing to the resistive dividing bridge. Alternatively, two additional resistances R, R? formed in the front face of the substrate making it possible to obtain the resistive dividing bridge independently of the capacitive dividing bridge.

Abstract: The invention relates to an electronic component with a high-electron-mobility heterojunction. The component includes a superposition of a first semiconductor layer and of a second semiconductor layer, to form an electron-gas layer in proximity to the interface between the first and second semiconductor layers, and first and second conductive metal electrode contacts formed on said second semiconductor layer plumb with the electron-gas layer. At least one of the first and second metal contacts has a contact length L such that L?1.5*?(?c/R2 Deg), where ?c is the specific resistance of the metal contact with the electron-gas layer at 425 K and R2 Deg is the sheet resistance in the electron-gas layer at 425 K.

Abstract: The invention aims for a polarisation circuit of a power component comprising a capacitive dividing bridge and a resistive dividing bridge formed on the same substrate as the component. An additional electrode 1? in the front face 100 of the substrate makes it possible to adjust one of the capacitance values of the capacitive dividing bridge according to the other of the capacitance values coming from one of the electrodes of the power component. The sizing of this additional electrode furthermore makes it possible to obtain a leakage resistance contributing to the resistive dividing bridge. Alternatively, two additional resistances R, R? formed in the front face of the substrate making it possible to obtain the resistive dividing bridge independently of the capacitive dividing bridge.

Abstract: The invention relates to an electronic component with a high-electron-mobility heterojunction. The component includes a superposition of a first semiconductor layer and of a second semiconductor layer, to form an electron-gas layer in proximity to the interface between the first and second semiconductor layers, and first and second conductive metal electrode contacts formed on said second semiconductor layer plumb with the electron-gas layer. At least one of the first and second metal contacts has a contact length L such that L?1.5*?(?c/R2 Deg), where ?c is the specific resistance of the metal contact with the electron-gas layer at 425 K and R2 Deg is the sheet resistance in the electron-gas layer at 425 K.

Abstract: An optoelectronic device including a light emitting component and a field-effect transistor, the optoelectronic device including a first semiconductor layer made of a III-V or II-VI compound doped a first conductivity type; an active layer of the light-emitting component; and a second semiconductor layer made of the III-V or III-VI compound doped a second conductivity type opposite the first type, the active layer being sandwiched between the first and second semiconductor layers, wherein the channel of the field-effect transistor is located in the first semiconductor layer, the first semiconductor layer being uninterrupted between the field-effect transistor and the lightemitting component.

Abstract: The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer (4), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer (6) on the first semiconductor layer so as to form an electron gas layer (5) at the interface between the first and second layers; and forming a control gate (75) over the second conductive layer (6) and vertically in line with the implanted area (8).

Abstract: An optoelectronic device including a light emitting component and a field-effect transistor, the optoelectronic device including a first semiconductor layer made of a III-V or II-VI compound doped a first conductivity type; an active layer of the light-emitting component; and a second semiconductor layer made of the III-V or III-VI compound doped a second conductivity type opposite the first type, the active layer being sandwiched between the first and second semiconductor layers, wherein the channel of the field-effect transistor is located in the first semiconductor layer, the first semiconductor layer being uninterrupted between the field-effect transistor and the lightemitting component.

Abstract: A high electron mobility heterojunction transistor, including a first GaN layer; a second, p-doped GaN layer on top of the first layer, including magnesium as a p-type dopant, the concentration of which is at least equal to 5*1016 cm?3 and at most equal to 2*1018 cm?3, the thickness of the second GaN layer being between 20 and 50 nm; a third, n-doped GaN layer on top of the second GaN layer in order to form a depleted p-n junction; a fourth GaN layer, which is not intentionally doped, on top of the third GaN layer; a semiconductor layer plumb with the fourth GaN layer, which is not intentionally doped, in order to form an electron gas layer.

Abstract: A high electron mobility field-effect transistor of normally-off type, including a first layer of GaN with P-type doping; a second layer of GaN with N-type doping formed on the first layer of GaN; a third layer of unintentionally doped GaN formed on the second layer of GaN; a semiconductor layer formed to form an electron gas layer; a cavity formed through the third layer of GaN, without reaching the bottom of the second layer of GaN; a gate including a conductive gate material and a gate insulation layer arranged in the cavity, the gate insulation layer electrically insulating the conductive gate material relative to the second and third layers of GaN.

Abstract: An enhancement-mode field-effect transistor comprising at least: a heterojunction formed by at least one first layer comprising GaN and at least one second layer comprising AlGaN; and a gate comprising P-doped diamond, such that a first part of the second layer of the heterojunction defining a channel of the transistor is arranged between the gate and the first layer of the heterojunction; and in which the first part of the second layer of the heterojunction has a thickness of between approximately 5 nm and 12 nm and an aluminium content of between approximately 15% and 20%.

Abstract: A high electron mobility heterojunction transistor, including a first GaN layer; a second, p-doped GaN layer on top of the first layer, including magnesium as a p-type dopant, the concentration of which is at least equal to 5*1016 cm?3 and at most equal to 2*1018 cm?3, the thickness of the second GaN layer being between 20 and 50 nm; a third, n-doped GaN layer on top of the second GaN layer in order to form a depleted p-n junction; a fourth GaN layer, which is not intentionally doped, on top of the third GaN layer; a semiconductor layer plumb with the fourth GaN layer, which is not intentionally doped, in order to form an electron gas layer.

Abstract: A high electron mobility field-effect transistor of normally-off type, including a first layer of GaN with P-type doping; a second layer of GaN with N-type doping formed on the first layer of GaN; a third layer of unintentionally doped GaN formed on the second layer of GaN; a semiconductor layer formed to form an electron gas layer; a cavity formed through the third layer of GaN, without reaching the bottom of the second layer of GaN; a gate including a conductive gate material and a gate insulation layer arranged in the cavity, the gate insulation layer electrically insulating the conductive gate material relative to the second and third layers of GaN.

Abstract: The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer (4), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer (6) on the first semiconductor layer so as to form an electron gas layer (5) at the interface between the first and second layers; and forming a control gate (75) over the second conductive layer (6) and vertically in line with the implanted area (8).