Abstract: This invention relates to a method and system for a collision free insertion and removal of circuit-switched channels in a self-adaptive transmission data structure carrying different classes of packet-switched traffic on a slotted Local Area Network (LAN). This network may have bus or ring topology. The different classes of traffic are asynchronous traffic (packet-switched), synchronous traffic (packet-switched, time sensitive), isochronous traffic (circuit-switched), and signalling on demand. The inventive self-adaptive transmission data structure permits an economic, flexible and bandwidth efficient integration of these different classes of traffic.

Abstract: A protocol and format for multiple accessing and transporting information in a Distributed Queue Dual Bus communications network includes count field in which stations can reserve multiple time slots for transporting data.

Abstract: In a communications network comprising two counterflowing busses (folded bus or dual bus) and a number of stations (N1, N2, N3) connected between them, a cyclic reservation and access technique is provided. A headend unit generates consecutive time slots for data transmission which are grouped in cycles. For each cycle, the headend first issues a reservation command (RES) with a cycle number and a reservation count which each station augments by the slot count required locally. Each station stores the cycle number with the requested slot count. The headend stores in a global reservation queue, for each returning reservation command, the cycle number and the accumulated reservation count. Later it issues a start command (ST) with the respective cycle number, and subsequently generates the required number of slots as indicated by the stored accumulated reservation count. The headend can issue additional confirm commands and reject commands for activating a backpressure mechanism.

Abstract: For encoding a stream of k-bit data bytes into a stream of m-bit code bytes satisfying given constraints, a coding principle and coder apparatus are disclosed which allow pipelined and parallel handling of the byte stream. Each data byte DB and an associated coder state indicator S are together converted into a code byte CB. The coder state indicator S(i) to be associated with a data byte DB(i) is obtained by logically combining the coder state indicator S(i-1) of the preceding data byte DB(i-1) and a state transition indicator T(i-1) derived from the latter. This allows the simultaneous generation of all coder state indicators S for a whole group (a word) of data bytes, thereby enabling the parallel and pipelined operation of the coder.

Abstract: In a controlled fiber-optic switch for selectably connecting or disconnecting the ends of first (13) and second (11) optical fibers, guiding and holding elements (2) hold said fibers' ends in opposite position and define two alternative switching positions for the first fiber's end. By activating means (8, 20) lateral bending forces are applied to the first fiber (13). The first fiber's free end becomes switched by altering the fiber's effective length between its fixation (5) and its guiding and holding elements (2). Switching movement is controlled by a guiding aperture (9) for lateral guidance of the first fiber (13). The free fiber end of the first fiber (13) is located on one side of the aperture (9). A bendable portion of the first fiber is located and fixed on the other side of the aperture. In the connect position, the first fiber (13) is kept under residual axial stress against the opposite end of the second fiber (11).

Abstract: A distributed queue multiple access technique is disclosed for a system comprising two counterflowing transmission busses (A,B), plural stations (i, j) connected between them, and a headend station generating slots on the first one (A) of the busses; each station transmitting access requests on the second one (B) of the busses and determining its right to transmit data in slots on the first bus on the basis of access requests it has seen. Each station maintains a FIFO queue (41) for sequential storage of numbers representing external (EXT-REQ) and local (LOC-REQ) access requests. To achieve correct timing between access requests entering the queue from the second bus and respective free slots passing a station on the first bus, a station-individual delay is introduced by maintaining in a FIFO delay storage (71) a specific number of entries. This results in an equally fair treatment for all stations, and guarantees the availability of consecutive free slots for any station which requested them.

Abstract: In a communication system providing multiple access to transmission facilities for a plurality of stations (17, 21), two separate networks (11, 13) are provided: One is a token ring (11) on which access tokens and data are transmitted, the other is a high-speed optical fiber transmission ring (13) on which only large-volume data blocks are transmitted between particular stations (21) which are attached to both rings, but no access information. A token manager (27) in the token ring (11) provides at regular intervals particular tokens that are only used by the particular stations (21) for obtaining access to the high-speed ring (13), but also provides other tokens for regulating access to the token ring (11) for other stations (17). Special access nodes (23) are provided which allow to connect the particular stations (21) to the high-speed ring (13) without extending its length.

Abstract: A phase locked loop (PLL) arrangement comprising a local crystal oscillator (23) and a tapped delay chain (15) of analog delay elements (17). Connected to the delay chain taps are a flash register (25) consisting of latches which store the tap signal values at each data signal transition, and an output multiplexer (37) for selecting one of the tap signals as phase shifted output clock. Contents of the flash register are encoded by an encoder (33) which furnishes a value representing the phase offset between data signal and local clock signal. By a look-up table (41), the phase offset is converted to a phase selection value controlling the output multiplexer. The delay chain serves two purposes: Phase offset detection and clock signal phase shifting. No sampling or control signals are used which have a higher frequency than that of the system clock.