Patents by Inventor Erwin Aguas Sangalang

Erwin Aguas Sangalang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit packaging system with leadframe and method of manufacture thereof
    Patent number: 8492887
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jayby Agno, Erwin Aguas Sangalang, Dexter Anonuevo, Ramona Damalerio
  • Integrated circuit packaging system with dual row lead-frame having top and bottom terminals and method of manufacture thereof
    Patent number: 8115287
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: February 14, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Abelardo Jr. Hadap Advincula, Erwin Aguas Sangalang, Lionel Chien Hui Tay
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110233743
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view.
    Type: Application
    Filed: March 25, 2010
    Publication date: September 29, 2011
    Inventors: Jayby Agno, Erwin Aguas Sangalang, Dexter Anonuevo, Ramona Damalerio
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH DUAL ROW LEAD-FRAME HAVING TOP AND BOTTOM TERMINALS AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20110140252
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming outer leads having outer terminal sections, the outer terminal sections having an upper terminal and a bottom terminal; forming inner leads having inner terminal sections wider than a distance between the outer terminal sections of the outer leads, and the inner terminal sections have an upper terminal and a bottom terminal; connecting an integrated circuit to the inner leads and the outer leads; and encapsulating the integrated circuit, the inner leads, and the outer leads with an encapsulation while leaving the upper terminals and the bottom terminals of the outer terminal sections and the upper terminals and bottom terminals of the inner terminal sections exposed from the encapsulation.
    Type: Application
    Filed: December 10, 2009
    Publication date: June 16, 2011
    Inventors: Zigmund Ramirez Camacho, Abelardo Jr. Hadap Advincula, Erwin Aguas Sangalang, Lionel Chien Hui Tay