Patents by Inventor Erwin Bacher

Erwin Bacher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240308264
    Abstract: A security element for documents of value or the like, has a substrate which has been coated with a heat-sealing adhesive that is non-tacky at room temperature and suitable for applying the security element to a substrate of a document of value. The heat-sealing adhesive contains a radiation-crosslinkable component and a reactive diluent.
    Type: Application
    Filed: January 12, 2022
    Publication date: September 19, 2024
    Inventors: Winfried HOFFMULLER, Christine HETTENKOFER, Erwin BACHER, Patrick RENNER
  • Publication number: 20220213651
    Abstract: Electroconductive paper structure with cellulosic fibrous materials and electroconductive fibers, wherein the electroconductive paper structure has embedded therein a continuous, electroconductive thread for contacting the electroconductive paper structure from one end to the opposite end of the paper structure.
    Type: Application
    Filed: April 27, 2020
    Publication date: July 7, 2022
    Inventors: Rudolf SEIDLER, Daniel LENSSEN, Maik Rudolf Johann SCHERER, Christoph HUNGER, Erwin BACHER
  • Patent number: 10090215
    Abstract: A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: October 2, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Patent number: 9799521
    Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: October 24, 2017
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Thomas Schweinboeck, Jesper Wittborn, Erwin Bacher, Juergen Holzmueller, Hans-Joachim Schulze
  • Publication number: 20170125315
    Abstract: A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.
    Type: Application
    Filed: January 11, 2017
    Publication date: May 4, 2017
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Patent number: 9583406
    Abstract: A method for semiconductor fabrication includes forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a singulation region and a contact region. The method also includes forming a first array of process control monitoring structures within the singulation region of a substrate. The method also includes forming a first array of contact pads disposed in the contact region. The method also includes forming electrical connections between the first array of process control monitoring structures and the first array of contact pads, wherein all external electrical connections to the first array of process control monitoring structures are made through the first array of contact pads.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Publication number: 20160276233
    Abstract: A method for semiconductor fabrication includes forming a first array of semiconductor circuitry and a second array of semiconductor circuitry separated by a singulation region and a contact region. The method also includes forming a first array of process control monitoring structures within the singulation region of a substrate. The method also includes forming a first array of contact pads disposed in the contact region. The method also includes forming electrical connections between the first array of process control monitoring structures and the first array of contact pads, wherein all external electrical connections to the first array of process control monitoring structures are made through the first array of contact pads.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 22, 2016
    Inventors: Andrew Christopher Graeme Wood, Gernot Fasching, Marius Aurel Bodea, Thomas Krotscheck Ostermann, Erwin Bacher
  • Publication number: 20160189964
    Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 30, 2016
    Inventors: Markus Zundel, Thomas Schweinboeck, Jesper Wittborn, Erwin Bacher, Juergen Holzmueller, Hans-Joachim Schulze
  • Patent number: 9306011
    Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: April 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Thomas Schweinboeck, Jesper Wittborn, Erwin Bacher, Juergen Holzmueller, Hans-Joachim Schulze
  • Patent number: 9142444
    Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 22, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Zundel, Erwin Bacher, Andreas Behrendt, Joerg Ortner, Walter Rieger, Rudolf Zelsacher
  • Publication number: 20150097184
    Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doping regions of a first doping structure arranged at a main surface of the semiconductor substrate and a plurality of second doping regions of the first doping structure arranged at the main surface of the semiconductor substrate. The first doping regions of the plurality of first doping regions of the first doping structure include dopants of a first conductivity type with different doping concentrations. Further, the second doping regions of the plurality of second doping regions of the first doping structure include dopants of a second conductivity type with different doping concentrations. At least one first doping region of the plurality of first doping regions of the first doping structure partly overlaps at least one second doping region of the plurality of second doping regions of the first doping structure causing an overlap region arranged at the main surface.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 9, 2015
    Inventors: Markus Zundel, Thomas Schweinboeck, Jesper Wittborn, Erwin Bacher, Juergen Holzmueller, Hans-Joachim Schulze
  • Publication number: 20130323905
    Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.
    Type: Application
    Filed: May 15, 2013
    Publication date: December 5, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Markus ZUNDEL, Erwin BACHER, Andreas BEHRENDT, Joerg ORTNER, Walter RIEGER, Rudolf ZELSACHER
  • Publication number: 20110294289
    Abstract: A method for producing a connection electrode for a first and second adjacent and complementarily doped semiconductor zones includes a step of producing a trench extending through the first semiconductor zone into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench. The method also includes producing a first connection zone in the first semiconductor zone by implanting dopant atoms into the sidewalls at least at a first angle. The method further includes producing a second connection zone in the second semiconductor zone by implanting dopant atoms at least at a second, different angle. The method also includes depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode.
    Type: Application
    Filed: November 23, 2010
    Publication date: December 1, 2011
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Walter Reiger, Paul Ganitzer, Oliver Haeberlen, Franz Hirler, Markus Zundel, Rudolf Zelsacher, Erwin Bacher
  • Patent number: 7851349
    Abstract: A method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone includes producing a trench extending through the first semiconductor zone right into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench. The method also includes applying a protective layer to a first one of the first and second semiconductor zones in the trench, and producing a first connection zone in the second of the two semiconductor zones, which is not covered by the protective layer. The method further includes depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: December 14, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Walter Rieger, Paul Ganitzer, Oliver Haeberlen, Franz Hirler, Markus Zundel, Rudolf Zelsacher, Erwin Bacher
  • Publication number: 20100078716
    Abstract: A semiconductor component comprises a semiconductor body with at least one protective trench in the semiconductor body. An insulation layer is situated at least at the bottom of the protective trench. An electrically conductive layer having a thickness D is formed on the insulation layer in the protective trench, wherein the electrically conductive layer only partly fills the protective trench.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Inventors: Erwin Bacher, Andreas Behrendt, Joerg Ortner, Walter Rieger, Rudolf Zelsacher, Markus Zundel
  • Patent number: 7601596
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming trenches in a first side of a semiconductor material and forming a thick oxide layer on the trenches and on the first side. A part of the first side and the trenches is masked using a first mask, and the semiconductor material is doped by implantation through the thick oxide layer while the first mask is present. At least part of the thick oxide layer is removed while the first mask remains.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: October 13, 2009
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler, Rudolf Zelsacher, Erwin Bacher
  • Publication number: 20080116511
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming trenches in a first side of a semiconductor material and forming a thick oxide layer on the trenches and on the first side. A part of the first side and the trenches is masked using a first mask, and the semiconductor material is doped by implantation through the thick oxide layer while the first mask is present. At least part of the thick oxide layer is removed while the first mask remains.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 22, 2008
    Applicant: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler, Rudolf Zelsacher, Erwin Bacher
  • Publication number: 20070093019
    Abstract: Method for producing a connection electrode for two semiconductor zones arranged one above another The invention relates to a method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone, which are arranged one above another and are doped complementarily with respect to one another, which method comprises the method steps of: producing a trench extending through the first semiconductor zone right into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench, applying a protective layer to one of the first and second semiconductor zones in the trench, producing a first connection zone in the other of the two semiconductor zones, which is not covered by the protective layer, by introducing dopant atoms into this other semiconductor zone via the trench, the connection zone being of the same conductivity type as said other semi
    Type: Application
    Filed: September 26, 2006
    Publication date: April 26, 2007
    Applicant: Infineon Technologies Austria AG
    Inventors: Walter Rieger, Paul Ganitzer, Oliver Haeberlen, Franz Hirler, Markus Zundel, Rudolf Zelsacher, Erwin Bacher
  • Patent number: 6613104
    Abstract: The invention relates to optical brighteners that possess at least one free SO3H group and their use for whitening materials containing cellulose.
    Type: Grant
    Filed: January 10, 2001
    Date of Patent: September 2, 2003
    Assignee: Bayer Aktiengesellschaft
    Inventors: Wolfgang Zarges, Rolf Brockmann, Erwin Bacher, Detlef Szeymies
  • Publication number: 20030089888
    Abstract: The invention relates to a method of optically brightening natural or synthetic materials with aqueous brightener preparations containing
    Type: Application
    Filed: September 20, 2002
    Publication date: May 15, 2003
    Inventors: Erwin Bacher, Rolf Brockmann, Heinz Giesecke, Reiner Gottschalk, Peter-Roger Nyssen