Abstract: Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.

Abstract: Methods, systems and computer program products for avoiding Boolean DRC failures during cell placement are provided. Aspects include generating a semiconductor layout by filling a plurality of rows within a macro block with cells including functional cells and fill cells. Aspects also include modifying the semiconductor layout by removing one or more fill cells from the macro block to create a gap. Aspects also include examining a set of cells that border edges of the gap to identify one or more predicted rule violations. Based on the identified one or more predicted rule violations, aspects also include modifying the semiconductor layout to change a shape of the gap to avoid the one or more predicted rule violations.

Abstract: Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.

Abstract: Methods, systems and computer program products for avoiding Boolean DRC failures during cell placement are provided. Aspects include generating a semiconductor layout by filling a plurality of rows within a macro block with cells including functional cells and fill cells. Aspects also include modifying the semiconductor layout by removing one or more fill cells from the macro block to create a gap. Aspects also include examining a set of cells that border edges of the gap to identify one or more predicted rule violations. Based on the identified one or more predicted rule violations, aspects also include modifying the semiconductor layout to change a shape of the gap to avoid the one or more predicted rule violations.

Abstract: Methods, systems and computer program products for providing fin-based fill cell optimization are provided. Aspects include receiving a semiconductor layout comprising at least a first logic cell, a second logic cell, and a fill cell. A left boundary of the fill cell is adjacent to the first logic cell and a right boundary of the fill cell is adjacent to the second logic cell. Aspects also include determining a number of active left fins, right fins, and active fill cell fins associated with FinFET structures of the first logic cell, second logic cell and fill cell, respectively. Aspects also include comparing the number of active fins to a set of fin rules. Responsive to determining that the semiconductor layout violates the set of fin rules, aspects include modifying the semiconductor layout to change the number of active fill cell fins to satisfy the set of fin rules.

Abstract: A technique relates to structuring a semiconductor device. First empty cells are placed against hierarchical boundaries of a macro block. Functional cells are added in the macro block. Remaining areas are filled with second empty cells in the macro block. Shape requirements are determined for the first empty cells and the second empty cells. The first and second empty cells are replaced with determined shape requirements.

Abstract: A technique relates to structuring a semiconductor device. First empty cells are placed against hierarchical boundaries of a macro block. Functional cells are added in the macro block. Remaining areas are filled with second empty cells in the macro block. Shape requirements are determined for the first empty cells and the second empty cells. The first and second empty cells are replaced with determined shape requirements.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Examples of techniques for automated attribute propagation and hierarchical consistency checking are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: detecting, by a processor, a non-standard extension during convergence of an integrated circuit logic design; propagating, by the processor, the non-standard extension to each level of a plurality of hierarchies of the integrated circuit design for which a net utilizes a special constraint; and verifying, by the processor, a hierarchy consistency across each level of the plurality of hierarchies.

Abstract: Aspects include techniques for selective boundary overlay insertion for hierarchical circuit design. A method may include determining, by a processing device, a block type of a child block. The method may further include electively inserting, by the processing device, at least one of an instantiated boundary overlay and a merged boundary overlay into the hierarchical circuit design based on the block type of the child block. The instantiated boundary overlay enables a parent block to pass a testing at an out-of-context level, and the merged boundary overlay enables the parent block to continue to pass the testing when the child block is inserted into the parent block associated with the child block.

Abstract: A method is provided for designing an integrated circuit utilizing an arrangement of at least one library cell having a plurality of parameterized input connection points disposed along a rod, a plurality of parameterized output connection points disposed along a wire and a cell structure to which the rod and wire are electrically connected; routing and making input and output connections to the library cells at the parameterized input connection points and the parameterized output connection points to satisfy design specifications of the integrated circuit. After determining which parameterized input connection points and parameterized output connection points are unused, the unused parameterized input connection points and parameterized output connection points are removed from each library cell of the integrated circuit design.

Abstract: In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.

Abstract: In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.