Patents by Inventor Erwin E. Yu
Erwin E. Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942159Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.Type: GrantFiled: February 2, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Chulbum Kim, Brian Kwon, Erwin E. Yu, Kitae Park, Taehyun Kim
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Patent number: 11915758Abstract: Memory devices might include a first storage element, a second storage element, a data line, and a controller. The first storage element is to store a first data bit. The second storage element is to store a second data bit. The data line is selectively connected to the first storage element, the second storage element, and a memory cell. The controller is configured to apply one of four voltage levels to the data line based on the first data bit and the second data bit.Type: GrantFiled: January 10, 2023Date of Patent: February 27, 2024Assignee: Micron Technology, Inc.Inventors: Hao T. Nguyen, Tomoko Ogura Iwasaki, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda, Aaron S. Yip, Yoshihiko Kamata
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Patent number: 11862257Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.Type: GrantFiled: November 17, 2022Date of Patent: January 2, 2024Assignee: Micron Technology, Inc.Inventors: Jun Xu, Violante Moschiano, Erwin E. Yu
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Publication number: 20230360709Abstract: A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
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Patent number: 11749353Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.Type: GrantFiled: May 16, 2022Date of Patent: September 5, 2023Assignee: Micron Technology, Inc.Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
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Publication number: 20230170016Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.Type: ApplicationFiled: January 12, 2023Publication date: June 1, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Dan Xu, Jun Xu, Erwin E. Yu, Paolo Tessariol, Tomoko Ogura Iwasaki
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Publication number: 20230078401Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.Type: ApplicationFiled: November 17, 2022Publication date: March 16, 2023Inventors: Jun Xu, Violante Moschiano, Erwin E. Yu
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Publication number: 20230063656Abstract: A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.Type: ApplicationFiled: February 2, 2022Publication date: March 2, 2023Inventors: Chulbum Kim, Brian Kwon, Erwin E. Yu, Kitae Park, Taehyun Kim
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Publication number: 20230066649Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.Type: ApplicationFiled: October 13, 2021Publication date: March 2, 2023Inventors: Erwin E. Yu, Surendranath C. Eruvuru, Yoshiaki Fukuzumi, Tomoko Ogura Iwasaki
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Publication number: 20230047662Abstract: A microelectronic device comprises a base structure, a memory array overlying the base structure, and a conductive pad tier overlying the memory array. The base structure comprises a logic region including logic devices. The memory array comprises vertically extending strings of memory cells within a horizontal area of the logic region of the base structure. The conductive pad tier comprises first conductive pads substantially outside of the horizontal area of the logic region of the base structure, and second conductive pads horizontally neighboring the first conductive pads and within the horizontal area of the logic region of the base structure. Memory devices and electronic systems are also described.Type: ApplicationFiled: August 13, 2021Publication date: February 16, 2023Inventors: Erwin E. Yu, Michele Piccardi, Surendranath C. Eruvuru
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Publication number: 20230039026Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.Type: ApplicationFiled: August 9, 2021Publication date: February 9, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Hao T. Nguyen, Tomoko Ogura Iwasaki, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda, Aaron S. Yip, Yoshihiko Kamata
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Patent number: 11562791Abstract: Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.Type: GrantFiled: August 9, 2021Date of Patent: January 24, 2023Assignee: Micron Technology, Inc.Inventors: Hao T. Nguyen, Tomoko Ogura Iwasaki, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda, Aaron S. Yip, Yoshihiko Kamata
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Patent number: 11557341Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.Type: GrantFiled: September 3, 2020Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Dan Xu, Jun Xu, Erwin E. Yu, Paolo Tessariol, Tomoko Ogura Iwasaki
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Patent number: 11557351Abstract: A device includes a memory array and a sense circuit coupled with the memory array. The sense circuit includes a sense node coupled with a data line of the memory array. A first sensing path includes a first transistor having a first gate coupled with the sense node. A second sensing path includes a second transistor having a second gate coupled with the sense node. A first threshold voltage of the first transistors differs from a second threshold voltage of the second transistor by a threshold voltage gap.Type: GrantFiled: April 19, 2021Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Luyen Tien Vu, Erwin E. Yu, Jeffrey Ming-Hung Tsai
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Publication number: 20220404408Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.Type: ApplicationFiled: August 24, 2022Publication date: December 22, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Dan Xu, Jun Xu, Erwin E. Yu
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Patent number: 11532367Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.Type: GrantFiled: December 8, 2020Date of Patent: December 20, 2022Assignee: MICRON TECHNOLOGY, INC.Inventors: Jun Xu, Violante Moschiano, Erwin E. Yu
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Patent number: 11442091Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to determine capacitance and/or resistance values of an access line in response to applying a reference current to the access line, wherein the access line is connected to control gates of memory cells of the array of memory cells.Type: GrantFiled: May 19, 2020Date of Patent: September 13, 2022Assignee: Micron Technology, Inc.Inventors: Dan Xu, Jun Xu, Erwin E. Yu
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Publication number: 20220277795Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Inventors: Kalyan Chakravarthy Kavalipurapu, Tomoko Ogura Iwasaki, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu
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Publication number: 20220208278Abstract: A device includes a memory array and a sense circuit coupled with the memory array. The sense circuit includes a sense node coupled with a data line of the memory array. A first sensing path includes a first transistor having a first gate coupled with the sense node. A second sensing path includes a second transistor having a second gate coupled with the sense node. A first threshold voltage of the first transistors differs from a second threshold voltage of the second transistor by a threshold voltage gap.Type: ApplicationFiled: April 19, 2021Publication date: June 30, 2022Inventors: Luyen Tien Vu, Erwin E. Yu, Jeffrey Ming-Hung Tsai
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Publication number: 20220180952Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventors: Jun Xu, Violante Moschiano, Erwin E. Yu