Abstract: A digital arithmetic combiner having improved overflow signal propagation delay characteristics is disclosed. Such an arithmetic combiner includes a tristate device having a data input terminal coupled to an overflow input terminal and a data terminal coupled to an overflow output terminal. A tristate control terminal is coupled to the output of logic circuitry. The logic circuitry is responsive to operand input signals and enables the tristate device to generate a signal at its data output terminal when the operand input signals have different logic states. In addition, an overflow generator is responsive to the operand input signals, and generates a signal indicating overflow conditions at the overflow output terminal when the operand input signals have the same logic state.

Abstract: When a positive or a negative overflow error condition is encountered, the present invention substitutes the most positive or most negative value for the erroneous sample. The sign bit of a potentially erroneous value is inverted to form the MSB of the substitute value, and this value is, in turn, inverted and expanded to form the n-l LSB's of the substitute value. If an overflow error condition is detected, the erroneous value is replaced by the substitute value.

Abstract: Color reference oscillator in a color television receiver comprises a non-inverting amplifier, with positive feedback from its output conveyed via a crystal filter to its input. A quadrature phase shift network, coupled to the filter output, develops phase shifted signals which are matrixed with signals derived directly from the non-inverting amplifier to form resultant signals with a phase intermediate the phases of the matrix inputs. Control voltage outputs of a phase comparator, responsive to oscillator signals and to received synchronizing bursts, determine the magnitude and polarity of the output of a controlled amplifier which has at its input the resultant signals produced by said matrixing. The controlled amplifier output, and the output of an inverting amplifier also responsive to said resultant signals, share the load resistor of the non-inverting amplifier.

Abstract: A frequency selective signal translating circuit is disclosed for use in a color television receiver including an automatic flesh tone color correction network which provides a reference signal for color demodulators of the receiver. The circuit comprises an input bandpass filter for attenuating unwanted frequency components from the reference signal output of the correction network. The filter is followed by a phase shifter for shifting the phase of the filtered reference signal as required for proper demodulator operation. The filter comprises a fixed alignment, single-tuned, series resonant circuit coupled in series between the correction network output and the demodulator reference signal inputs.

Abstract: An integratable third harmonic signal generator comprises an amplitude limiting amplifier, a linear amplifier, and a signal combining network. A sinusoidal input signal is coupled to the limiter and linear amplifiers. The limiting amplifier generates a square wave signal containing a first harmonic (fundamental) component at the frequency of the input signal, and higher order odd harmonics including a desired third harmonic frequency. The signal gain of the linear amplifier is set so that the magnitude of the output signal from the linear amplifier is sufficient to cancel with the first harmonic of the square wave output signal from the limiter amplifier, when these output signals are combined in the combining network. A resulting signal developed at the output of the combining network contains the desired third harmonic component, as well as higher order harmonics at acceptably reduced levels relative to the third harmonic component, to the substantial exclusion of the first harmonic component.

Abstract: An arrangement for symmetrically gain controlling a differential amplifier is disclosed. A control circuit including first and second similarly arranged transistors coupled between points of operating potential develops first and second control voltages of prescribed magnitude at collector outputs of the transistors. The first transistor is biased to provide the first control voltage at a fixed, prescribed level related to the gain control bias requirements of the amplifier. The second control voltage varies symmetrically with respect to the first control voltage in response to the setting of a potentiometer coupled to a bias circuit of the second transistor.

Abstract: A circuit for generating a composite keying signal comprises a burst gate circuit and a voltage translating network in a color television receiver also including keyed signal processing circuits and means for deriving horizontal and vertical blanking signals and a horizontal sync signal from a composite color television signal containing a color burst component. The burst gate circuit responds to the horizontal sync signal to develop a burst gate pulse encompassing the burst interval. A voltage level developed by the translating network in response to the horizontal and vertical blanking signals is combined with the burst gate pulse to produce a composite keying signal. The composite keying signal comprises a first pulse component of a desired level as determined by the translating network and ocurring during the blanking intervals, and a second pulse cmponent as provided from the burst gate circuit, superimposed on the first pulse and encompassing the burst interval.

Abstract: An automatic kinescope beam current limiter for a television receiver comprises a source of signal representative of kinescope beam current conduction, a first transistor responsive to the representative signal over first, second and third ranges of excessive beam currents above a threshold level, and a second transistor. A first control signal derived from the first transistor modifies the video signal peak-to-peak amplitude (contrast level) when beam currents above the threshold level occur. The output of the first transistor is selectively coupled to an input of the second transistor when beam currents beyond the first range occur. A second control signal derived from the second transistor modifies the video signal D.C. component (brightness level) to limit beam currents beyond the first range, whereby both the peak amplitude and D.C. components are modified over the second range.

Abstract: A controlled oscillator comprises an amplifier including an active device, a filter network arranged in a feedback loop of the amplifier for providing regenerative feedback to sustain oscillation of the amplifier, and a source of control signals. Output oscillatory signals from the amplifier and output control signals from the control source are summed by a combining network to produce a resultant controlled signal, which is coupled to the filter network. Parasitic capacitances associated with output terminals of the amplifier and control source impart an unwanted phase shift to the controlled signal. A compensation signal derived from the oscillator is supplied to the combining network with a magnitude and phase to offset the unwanted phase shift, to thereby produce a phase compensated resultant controlled signal.

Abstract: A sample and hold detector arrangement suitable for construction in integrated circuit form as an automatic chroma gain control detector, or a color oscillator AFPC detector, or the like. A wide bandwidth analog multiplier circuit is supplied with an intermittent reference signal and a second signal, the phase or amplitude of which is to be sampled. In a preferred embodiment, the reference signal corresponds to the burst component of a composite color television signal and the second signal corresponds to a locally generated color subcarrier signal. The multiplier provides oppositely phased output signals which are coupled to first and second sample and hold circuits. Each sample and hold circuit is keyed to concurrently sample the respective multiplier outputs for the same sampling interval, and each provides substantially symmetrical bidirectional conduction to associated filter capacitors during the sampling interval and a high holding impedance during the remainder of each cycle.

Abstract: Brightness control apparatus for a video signal image reproducing system including a video signal processing channel, a kinescope driver for supplying video signals to an image reproducing kinescope, and a source of substantially fixed potential to which signals processed by the kinescope driver are referenced. A comparator senses the substantially fixed reference potential and a blanking level which occurs during periodic blanking intervals of the video signal, and provides an output control signal indicative of the voltage difference between the reference potential and the blanking level. The control voltage is applied to the video channel for translating the blanking level in a direction to minimize the voltage difference, to thereby establish the conduction of the kinescope driver during image intervals of the video signal at a level corresponding to a desired image black level condition when such condition is manifested by the video signal.

Abstract: Brightness control apparatus in a video system employing a sample and hold circuit including a charge storage capacitor. The sample and hold circuit forms a closed control loop with a signal processing channel, and is keyed during periodic blanking intervals of the video signal to sample the magnitude of a reference voltage and a brightness representative blanking level of the video signal. The sample and hold circuit provides an output control signal indicative of the voltage difference between the reference voltage and the blanking level. The control signal is applied to the signal channel for translating the blanking level in a direction to minimize the voltage difference, so that a desired relationship between the reference voltage and the blanking level is preserved.