Abstract: A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up hardness of the n-channel and p-channel field effect transistors while retaining good transistor properties by incorporating a further epitaxial layer and highly doped implantation regions into a lower epitaxial layer from which the wells are generated by out-diffusion into the upper epitaxial layer. In addition to achieving optimum transistor properties, the reduced lateral diffusion provided enables a lower n.sup.+ /p.sup.+ spacing, and thus achieves a higher packing density with improved latch-up hardness.

Abstract: A memory cell comprises a double gate field effect transistor which exhibits source and drain regions located in a semiconductor body and two gate electrodes covering the semiconductor area between the source and drain regions, the gate electrodes being separated from the semiconductor body by a multilayer insulation. The first gate electrode is a memory gate, whereas inversion layers are produced with the second gate electrode given supply of a gate voltage, the inversion layers extending the source and drain regions in the direction towards the memory gate. The structure provides a surface-saving design of a selection element. The second gate electrode is employed for this purpose as the selection element and is connected to a selection line (word line). The invention finds application in very large scale integrated semiconductor memories.

Abstract: Analog or digital MOS circuits in VLSI technology are produced by a method in which the manufacture of two troughs (5, 8) occurs with only one mask (3) used in production of the p-trough (5). The n-trough (8) is formed by a surface-wide implantation (7) of an ion selected from a group consisting of P, As and Sb. The channel implantation of the p-transistors occurs simultaneously. The field (11) and channel (12) implantation of the n-channel transistors is carried out with a silicon nitride mask (9), i.e., a LOCOS mask, and a double boron implantation (10a, 10b). The field implantation (16) of the p-channel transistors is carried out with arsenic (15). Advantages of this process sequence include reduction of parasistic edge capacitances at the source/drain edges with fewer masking steps.

Abstract: Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations (FIG. 3, 8 and FIG. 5, 10) occur with only one mask (7a). This mask (7a), which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors (9). The source/drain implantation (10) for the p-channel transistors (11) occurs without a mask and the oxide layer thickness, d.sub.6, over the source/drain regions of the n-channel transistors (9) functions as a masking layer. An advantage of this process sequence is that switched capacitor structures (FIG. 6, 5b, 12) can be simultaneously produced whereby the oxide layer thickness, d.sub.4, over the polysilicon-1 level (5a, 5b) determines the thickness of the insulating layer, d.sub.cox, of the capacitor structures (5b, 12).

Abstract: The invention provides a method for manufacturing adjacent tubs implanted with dopant material ions in the manufacture of LSI complementary MOS field effect transistor circuits (CMOS circuits), and also provides a method sequence for a CMOS process adapted to tub manufacture. In accordance with the principles of the invention, for the greatest possible spatial separation of the tubs, a p-tub (5) is produced before a n-tub (8) and an undercutting (25) of a nitride layer (4) serving as the implantation mask in the p-tub production is intentionally produced, so that, during a subsequent oxidation, the edge of the oxidation is shifted toward the outside by about 1 to 2 .mu.m. Further, the penetration depth x.sub.jn of the n-tub (8) is set smaller by a factor at least equal to 4 relative to the penetration depth x.sub.jp of the p-tub (5), whereby the thickness of the n-doped epitaxial layer (2) and the penetration depth x.sub.jp are about matched to one another. The two tubs are separately implanted and diffused.

Abstract: A method for manufacturing MNOS memory transistors with very short channel lengths in silicon gate technology. In a substrate of a first semiconductor type, source and drain zones of MNOS and MOS components of a second conductivity type opposite the first conductivity type are provided. The edges of gate electrodes, with reference to the plane of the substrate surface, lie perpendicularly and self-adjusting over the edges of the source and drain zones, whereby the source and drain zones generated in the substrate are manufactured by means of ion implantation upon employment of the gate electrodes as the implantation mask.

Abstract: The invention relates to a MNOS memory cell arrangement in VLSI (very large scale integration) technology comprised of a multi-layer gate insulating layer covering a surface of a semiconductor body in the region between the source and drain zones. In order to avoid breakdowns at the source and drain zone edges before an erasure voltage is attained, the gate electrode is split into two electrodes, which can be operated in different ways and which are superimposed on upon another. These gate electrodes are connected via self-aligned, overlapped contacts. This arrangement resolves "short channel erasure", even in the case of VLSI technology. The invention can be applied as required to MNOS EEPROM memory devices.

Abstract: Integrated MOS circuits with and without MNOS memory transistors in silicon-gate technology are produced with overlapped contacts using a silicon nitride mask. After production of structured SiO.sub.2 layers on a p- or n- doped semiconductor substrate to separate active transistor zones in accordance with the so-called LOCOS process, a silicon nitride layer is deposited onto the surface and is then structured so that the zones in which a gate oxide is to be produced, are uncovered and during gate oxidation, the surface of this structured silicon nitride layer is converted into an oxynitride layer. In contrast to previously known processes, the invention provides self-aligned overlapped contacts with oversized contact holes. The silicon-nitride layer functions as an etch-stop during etching of an intermediate oxide. This avoids under-etching of the polysilicon during contact hole etching. The overlapped contacts allow a substantial increase in the packing and integration density of the so-produced circuits.

Abstract: An integrated multi-layer insulator memory cell is produced via silicon-gate technology, with self-adjusting, overlapping polysilicon contact wherein a gate oxide of a peripheral transistor is produced after the application of multi-layer insulating layer comprised of a storage layer and a "blocking" layer. The "blocking" layer consists of an oxynitride layer formed by oxidation of a silicon nitride layer surface or an additionally applied SiO.sub.2 layer and has a layer thickness of about 5 to 30 nm. Such "blocking" layer prevents an undesired injection of charge carriers from the silicon-gate electrode. It also provides means for forming a self-adjusting, overlapping polysilicon contact.

Abstract: A static storage element in a field effect transistor arrangement, has source and drain zones in a semiconductor body and a gate insulation layer provided on the surface of the semiconductor body. A spatial region having a high lattice defect or trap density is formed in the gate insulation layer for storing a quantity of charge which can be altered by electromagnetic radiation.