Patents by Inventor Erwin Lercher

Erwin Lercher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11387359
    Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: July 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Oliver Humbel, Josef-Georg Bauer, Jens Brandenburg, Diana Car, Philipp Sebastian Koch, Angelika Koprowski, Sebastian Kremp, Thomas Kurzmann, Erwin Lercher, Holger Ruething
  • Patent number: 10727311
    Abstract: A method for forming a power semiconductor device is provided. The method includes: providing a semiconductor wafer grown by a Czochralski process and having a first side; forming an n-type substrate doping layer in the semiconductor wafer at the first side, the substrate doping layer having a doping concentration of at least 1017/cm3; and forming an epitaxy layer on the first side of the semiconductor wafer after forming the n-type substrate doping layer.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Johannes Konrad Baumgartl, Matthias Kuenle, Erwin Lercher, Daniel Schloegl
  • Publication number: 20200194585
    Abstract: A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 ?m. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 18, 2020
    Inventors: Oliver Humbel, Josef-Georg Bauer, Jens Brandenburg, Diana Car, Philipp Sebastian Koch, Angelika Koprowski, Sebastian Kremp, Thomas Kurzmann, Erwin Lercher, Holger Ruething
  • Patent number: 10243066
    Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn).
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: March 26, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Daniel Schloegl, Johannes Baumgartl, Matthias Kuenle, Erwin Lercher, Hans-Joachim Schulze, Christoph Weiss
  • Publication number: 20190035909
    Abstract: A method for forming a power semiconductor device is provided. The method includes: providing a semiconductor wafer grown by a Czochralski process and having a first side; forming an n-type substrate doping layer in the semiconductor wafer at the first side, the substrate doping layer having a doping concentration of at least 1017/cm3; and forming an epitaxy layer on the first side of the semiconductor wafer after forming the n-type substrate doping layer.
    Type: Application
    Filed: July 31, 2018
    Publication date: January 31, 2019
    Inventors: Gerhard Schmidt, Johannes Baumgartl, Matthias Kuenle, Erwin Lercher, Daniel Schloegl
  • Patent number: 10079281
    Abstract: A method for forming a semiconductor device includes incorporating dopants of a first conductivity type into a nearby body region portion of a semiconductor substrate having a base doping of the first conductivity type. The incorporation of the dopants of the first conductivity type is masked by a mask structure at at least part of an edge region of the semiconductor substrate. The method further includes forming a body region of a transistor structure of a second conductivity type in the semiconductor substrate. The nearby body region portion of the semiconductor substrate is located adjacent to the body region of the transistor structure.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: September 18, 2018
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Erwin Lercher
  • Publication number: 20170243940
    Abstract: A method for forming a semiconductor device includes incorporating dopants of a first conductivity type into a nearby body region portion of a semiconductor substrate having a base doping of the first conductivity type. The incorporation of the dopants of the first conductivity type is masked by a mask structure at at least part of an edge region of the semiconductor substrate. The method further includes forming a body region of a transistor structure of a second conductivity type in the semiconductor substrate. The nearby body region portion of the semiconductor substrate is located adjacent to the body region of the transistor structure.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 24, 2017
    Inventors: Gerhard Schmidt, Erwin Lercher
  • Publication number: 20170243963
    Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn).
    Type: Application
    Filed: May 8, 2017
    Publication date: August 24, 2017
    Applicant: Infineon Technologies AG
    Inventors: Daniel Schloegl, Johannes Baumgartl, Matthias Kuenle, Erwin Lercher, Hans-Joachim Schulze, Christoph Weiss
  • Patent number: 9647083
    Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn).
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Schloegl, Johannes Baumgartl, Matthias Kuenle, Erwin Lercher, Hans-Joachim Schulze, Christoph Weiss
  • Publication number: 20160322472
    Abstract: A method of producing a semiconductor device is presented. The method comprises: providing a semiconductor substrate having a surface; epitaxially growing, along a vertical direction (Z) perpendicular to the surface, a back side emitter layer on top of the surface, wherein the back side emitter layer has dopants of a first conductivity type or dopants of a second conductivity type complementary to the first conductivity type; epitaxially growing, along the vertical direction (Z), a drift layer having dopants of the first conductivity type above the back side emitter layer, wherein a dopant concentration of the back side emitter layer is higher than a dopant concentration of the drift layer; and creating, either within or on top of the drift layer, a body region having dopants of the second conductivity type, a transition between the body region and the drift layer forming a pn-junction (Zpn).
    Type: Application
    Filed: April 29, 2016
    Publication date: November 3, 2016
    Inventors: Daniel Schloegl, Johannes Baumgartl, Matthias Kuenle, Erwin Lercher, Hans-Joachim Schulze, Christoph Weiss