Abstract: A method for forming a semiconductor device includes forming a first gate electrode over a semiconductor substrate, wherein the first gate electrode comprises silicon and forming a second gate electrode over the semiconductor substrate and adjacent the first gate electrode, wherein the second gate electrode comprises silicon. Nanoclusters are present in the first gate electrode. A peripheral transistor area is formed devoid of nanoclusters.

Abstract: A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.

Abstract: A method for making a multibit non-volatile memory cell structure is provided herein. In accordance with the method, a semiconductor substrate (101) is provided, and first and second sets of memory stacks (103, 105, 107, and 109) are formed on the substrate, each memory stack comprising a control gate (111) and a layer of memory material (113). A source/drain region (123) is then formed between the first and second sets of memory stacks, and a silicide layer (125) is formed over the source/drain region.

Abstract: A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

Abstract: A split gate storage device includes a first gate electrode in contact with a first gate dielectric and a second gate electrode in contact with a second gate dielectric. A first diffusion region underlies a portion of a trench defined in a semiconductor substrate and a second diffusion region occupies an upper portion of the substrate. A first gate dielectric lines the trench. One of the first and second gate dielectrics includes a layer of discontinuous storage elements (DSEs) and one of the first and second gate electrodes is located at least partially within the trench. In one case, the first gate electrode is a control gate and the first dielectric contains the layer of DSEs. In another case, the first gate electrode is a select gate and the second dielectric contains the layer of DSEs. The second gate dielectric lies over an upper surface of the substrate.

Abstract: A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.

Abstract: A virtual ground memory array (VGA) is formed by forming source/drain lines using a patterned photoresist layer over a sacrificial layer. The sacrificial layer is opened according to the pattern of the patterned photoresist layer. The openings are implanted to form the source/drain lines then filled with a conformal layer of dielectric material that can be etched selective to the sacrificial layer. A chemical mechanical polishing (CMP) step is then performed until the top of the sacrificial layer is exposed. Without requiring a mask, the sacrificial layer is etched away while leaving the dielectric material over the source/drain lines. The removal of the sacrificial layer exposes the substrate between the source/drain lines. A gate dielectric and storage layer is formed between the source drain lines and over the dielectric material. The word line is then formed over the gate dielectric and storage layer.

Abstract: In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

Abstract: A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.

Abstract: A non volatile memory (100) includes an array (102) of transistors (30) having discrete charge storage elements (40). The transistors are programmed by using a two step programming method (60) where a first step (68) is hot carrier injection (HCI) programming with low gate voltages. A second step (78) is selectively utilized on some memory cells to modify the injected charge distribution to enhance the separation of charge distribution between each memory bit within the transistor memory cell. The second step of programming is implemented without adding significant additional time to the programming operation. In one example, the first step injects electrons and the second step injects holes. The resulting distribution of the two steps removes electron charge in the central region of the storage medium.

Abstract: Method for measuring the properties of a slider/disk interface in a magnetic disk storage apparatus by measuring a triboelectric current flowing between disk and slider. Rotational speed is adjusted between 100 and 500 rpm so as to obtain a frictional contact between disk and slider. The shape of the tribo current curve obtained during the measuring time interval is analyzed. An early maximum of the tribo current amplitude and a subsequent continual decay indicates a good slider/disk interface and a long lifetime.

Abstract: In the manufacture of chip board panels, the chip parts are sprayed with a bonding agent, and in the subject process, a curtain of chip particles of rotational symmetry relative to a vertical axis is first coated with the sprayable binder, after which the particles fall onto a generally horizontal rotating plate, whereby the particles are deflected and slung outwardly where the particles are again exposed to the effect of the spray jet. Thereafter, the particles are deflected downward for further treatment or collected and removed. The apparatus includes a circular particle delivery part for the formation of the rotationally symmetrical curtain, a spray device arranged within the curtain and concentric to it, and a rotating plate supported concentrically to the axis of the curtain particles and spaced away from the feed point of the particles.