Patents by Inventor Erwin Robert Schlag

Erwin Robert Schlag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-phase frequency divider having one or more delay latches
    Patent number: 8791729
    Abstract: A multi-phase frequency divider comprises first and second latches configured to receive a first input clock having a first frequency and a first phase, wherein the second latch receives the inverted first input clock. The first and second latches generate a plurality of output clocks each having a frequency that equals the first frequency divided by a predetermined divider ratio. The plurality of output clocks each have different phases staggered from the first phase. The frequency divider also comprises at least a first delay latch electrically connected between the first and second latches. The first delay latch is configured to generate, based on an output clock generated by the first latch and a second input clock at the first frequency and a second phase, two delayed output clocks. These two delayed output clocks have a frequency that equals the first frequency divided by the predetermined ratio with different staggered phases.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 29, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Joachim Heinz Dieter Woelk, Erwin Robert Schlag
  • Mulit-Phase Frequency Divider Having One or More Delay Latches
    Publication number: 20130328600
    Abstract: A multi-phase frequency divider comprises first and second latches configured to receive a first input clock having a first frequency and a first phase, wherein the second latch receives the inverted first input clock. The first and second latches generate a plurality of output clocks each having a frequency that equals the first frequency divided by a predetermined divider ratio. The plurality of output clocks each have different phases staggered from the first phase. The frequency divider also comprises at least a first delay latch electrically connected between the first and second latches. The first delay latch is configured to generate, based on an output clock generated by the first latch and a second input clock at the first frequency and a second phase, two delayed output clocks. These two delayed output clocks have a frequency that equals the first frequency divided by the predetermined ratio with different staggered phases.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 12, 2013
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Joachim Heinz Dieter Woelk, Erwin Robert Schlag