Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: Implementations are presented herein that relate to a standard cell including a measuring structure for controlling process parameters during manufacture of an integrated circuit. A standard cell is formed in a plurality of material layers of an integrated circuit to perform part of a function of the integrated circuit, wherein the plurality of material layers is configured to be patterned by a plurality of mask layers during manufacture of the integrated circuit, wherein the standard cell includes a measuring structure that is placed within boundaries of the standard cell, wherein the measuring structure includes at least one feature in at least one of the plurality of material layers and the plurality of mask layers, wherein the at least one feature is configured to provide measurement results in order to control process parameters during manufacture of one of the material layers and mask layers.

Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).

Abstract: A process of manufacturing a semiconductor circuit includes providing a substrate layer, forming a metal layer above the substrate layer, incorporating circuit components in the substrate layer, and electrically connecting the circuit components to the metal layer. The process includes configuring the circuit components to perform an electrical function of the semiconductor circuit. The semiconductor circuit has a specific electrical conductivity between the substrate layer and the metal layer based on the electrical function performed. The process includes increasing the electrical conductivity between the substrate layer and the metal layer compared with the specific electrical conductivity.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: Implementations are presented herein that relate to a standard cell including a measuring structure.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame; generating a next level frame, the next level frame including the first level frame and a next level fill area outside of the first level frame; and adding a conductor to the next level frame. The conductor is connected to the electrical component, a first portion of the conductor is in the first level frame and a second portion of the conductor is in the next level fill area.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: A multi-pass method for designing at least a portion of a circuit layout on a substrate is provided which includes receiving or generating a first level frame including an electrical component; generating a fill pattern on the first level frame outside of a forbidden area of said first level frame; generating a next level frame, the next level frame including the first level frame and a next level fill area outside of the first level frame; and adding a conductor to the next level frame. The conductor is connected to the electrical component, a first portion of the conductor is in the first level frame and a second portion of the conductor is in the next level fill area.

Abstract: A process of manufacturing a semiconductor circuit includes providing a substrate layer, forming a metal layer above the substrate layer, incorporating circuit components in the substrate layer, and electrically connecting the circuit components to the metal layer. The process includes configuring the circuit components to perform an electrical function of the semiconductor circuit. The semiconductor circuit has a specific electrical conductivity between the substrate layer and the metal layer based on the electrical function performed. The process includes increasing the electrical conductivity between the substrate layer and the metal layer compared with the specific electrical conductivity.

Abstract: The invention relates to a semiconductor circuit arrangement having a semiconductor substrate, a first doping region, a second doping region, a connection doping region, an insulation layer and an electrically conductive structure which is to be planarized, it being possible for the charge carriers formed during a planarization step to be reliably dissipated, and for dendrite formation to be prevented, by a discharge doping region formed in the first and second doping regions.

Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).