Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.

Abstract: A complementary magnetic memory cell includes: a heavy metal film or an antiferromagnetic film, a first magnetic tunnel junction, a second magnetic tunnel junction, a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode; wherein the first magnetic tunnel junction and the second magnetic tunnel junction are fabricated above the heavy metal film or the antiferromagnetic film; the first electrode, the second electrode and the third electrode are fabricated under the heavy metal film or the antiferromagnetic film; the fourth electrode is fabricated above the first magnetic tunnel junction, and the fifth electrode is fabricated above the second magnetic tunnel junction; to store one bit of data, the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in a pair of complementary resistance states, wherein one magnetic tunnel junction is set to a high resistance state and the other remains unchanged.

Abstract: A highly reliable STT-MRAM structure and an implementation method thereof are provided. The STT-MRAM structure includes: a memory block array, including a plurality of memory blocks; on-chip in-situ temperature sensors, for detecting an instantaneous temperature of each memory block; and a controller, which outputs a reading or writing operation signal based on the instantaneous temperature of each memory block detected by the on-chip in-situ temperature sensors, so as to modulate respective voltages and/or frequencies of reading and writing operations of each memory block. When the instantaneous temperature is too high, the voltages and/or frequencies of the reading and writing operations would be decreased, to the contrary when the instantaneous temperature is too low, the voltages and/or frequencies of the reading and writing operations would be increased, which expands a reliable working temperature range and lengthens a lifetime of the STT-MRAM structure.

Abstract: A complementary magnetic memory cell includes: a heavy metal film or an antiferromagnetic film, a first magnetic tunnel junction, a second magnetic tunnel junction, a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode; wherein the first magnetic tunnel junction and the second magnetic tunnel junction are fabricated above the heavy metal film or the antiferromagnetic film; the first electrode, the second electrode and the third electrode are fabricated under the heavy metal film or the antiferromagnetic film; the fourth electrode is fabricated above the first magnetic tunnel junction, and the fifth electrode is fabricated above the second magnetic tunnel junction; to store one bit of data, the first magnetic tunnel junction and the second magnetic tunnel junction are arranged in a pair of complementary resistance states, wherein one magnetic tunnel junction is set to a high resistance state and the other remains unchanged.