Abstract: Emitter panels and displays utilizing solid state packages and methods for fabricating the same are disclosed. One emitter panel comprises a raised barrier on a submount defining a plurality of cavities, each cavity having at least one LED in a pixel area. The panel is capable of receiving electrical signals for independently controlling the emission from the emitters. Solid state displays utilize the emitter panels mounted in relation to one another to generate a message or image. The panels comprise multiple pixels each having at least one light emitter, with each panel capable of receiving electrical signals for independently controlling the emission of at the pixels.

Abstract: Emitter panels and displays utilizing solid state packages and methods for fabricating the same are disclosed. One emitter panel comprises a raised barrier on a submount defining a plurality of cavities, each cavity having at least one LED in a pixel area. The panel is capable of receiving electrical signals for independently controlling the emission from the emitters. Solid state displays utilize the emitter panels mounted in relation to one another to generate a message or image. The panels comprise multiple pixels each having at least one light emitter, with each panel capable of receiving electrical signals for independently controlling the emission of at the pixels.

Abstract: A method and apparatus for making in situ measurements of process parameters in the adverse environment of manufacturing processes such as silicon wafer processing. Rather than using surrogate “smart wafers” that limit the ranges of processing parameters to those that allow the measuring circuitry to survive the process, the present method mounts, on the actual wafer, an enclosed, shielded apparatus in which the electronic circuitry is protected from the adverse effects of conditions such as high temperatures, electromagnetic radiation and plasmas. The wafer plus the mounted apparatus is then transported through the entire process cycle and measurements are made and recorded.

Abstract: Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

Abstract: A method for forming a barrier layer upon an electrode contact. There is first provided a silicon substrate layer having an electrode contact region formed within the silicon substrate layer. There is then formed over the silicon substrate layer a titanium layer, where the titanium layer contacts the electrode contact region of the silicon substrate layer. There is then processed thermally the titanium layer in a nitrogen containing atmosphere to form a titanium silicide layer in contact with the electrode contact region and a titanium nitride layer formed thereover, where the titanium layer is completely consumed in forming the titanium silicide layer and the titanium nitride layer. Finally, there is formed upon the titanium nitride layer a barrier layer.

Abstract: Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

Abstract: A new method of polishing very large diameter wafers. Multiple polishing pads are provided. Each polishing pad rotates around the Z-axis. Each pad can be individually controlled for Chemical Mechanical Planarization (CMP) process parameters such as pressure, rotation speed, slurry feed and slurry mixture. The planarization process can be controlled or optimized by individual rotating polishing pad or by a grouping of one or more rotating polishing pads. The wafer being processed can be rotated which further reduces the dependence on existing pad conditions which in turn translates into reduced use of slurry and prolonged life-time of the polishing pad.

Abstract: Form a semiconductor device with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into emitter, NMOS and PMOS areas. Form a gate oxide layer above the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer above the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate.

Abstract: Disclosed is a method of fabricating a semiconductor field effect transistor, wherein the gate has a short foot portion in contact with the semiconductor substrate for a short gate length and consequent low capacitance, and a large amount of metal in a contact portion for low gate resistance. Salicides are formed on the T-gate source on drain contact areas resulting in large, low resistance contact areas.

Abstract: The process of the present invention can be used for conventional processing or for the Damascene process. The key concept of the present invention is a functional "filler" material which can later be removed (decomposed) to leave an air gap between the conducting lines. The filler material can be deposited as a step during conventional metal etch processing or it can be deposited as a first step of the processing of a semiconductor wafer. Leakage currents can be reduced as part of the present invention by applying passivation layers.

Abstract: A method for fabricating a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed horizontally spaced over the substrate a plurality of patterned microelectronics structures. There is then formed over the substrate and the plurality of patterned microelectronics structures a microelectronics layer. The microelectronics layer has a first region of the microelectronics layer interposed between the plurality of patterned microelectronics structures and a second region of the microelectronics layer not interposed between the plurality of microelectronics structures. Finally, there is processed through a grazing angle method the microelectronics layer, where the grazing angle method processes substantially all of the second region of the microelectronics layer without substantially processing the first region of the microelectronics layer.