Patents by Inventor Esa Hussa

Esa Hussa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10509440
    Abstract: A bendable display assembly comprises a plurality of layered elements each having two side surfaces, each having an area, the elements comprising a display element capable of displaying an adjustable visual output. Two successive elements of the plurality of layered elements have opposite side surfaces facing towards each other, the opposite side surfaces being, for a majority of their areas, in contact with a sealed sliding fluid volume extending between the successive elements, whereby the successive elements are slidably movable relative to each other when the display assembly is bent.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: December 17, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Esa Hussa
  • Publication number: 20170277226
    Abstract: A bendable display assembly comprises a plurality of layered elements each having two side surfaces, each having an area, the elements comprising a display element capable of displaying an adjustable visual output. Two successive elements of the plurality of layered elements have opposite side surfaces facing towards each other, the opposite side surfaces being, for a majority of their areas, in contact with a sealed sliding fluid volume extending between the successive elements, whereby the successive elements are slidably movable relative to each other when the display assembly is bent.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventor: Esa HUSSA
  • Patent number: 9684339
    Abstract: A bendable display assembly comprises a plurality of layered elements each having two side surfaces, each having an area, the elements comprising a display element capable of displaying an adjustable visual output. Two successive elements of the plurality of layered elements have opposite side surfaces facing towards each other, the opposite side surfaces being, for a majority of their areas, in contact with a sealed sliding fluid volume extending between the successive elements, whereby the successive elements are slidably movable relative to each other when the display assembly is bent.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: June 20, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Esa Hussa
  • Publication number: 20160224066
    Abstract: A bendable display assembly comprises a plurality of layered elements each having two side surfaces, each having an area, the elements comprising a display element capable of displaying an adjustable visual output. Two successive elements of the plurality of layered elements have opposite side surfaces facing towards each other, the opposite side surfaces being, for a majority of their areas, in contact with a sealed sliding fluid volume extending between the successive elements, whereby the successive elements are slidably movable relative to each other when the display assembly is bent.
    Type: Application
    Filed: February 3, 2015
    Publication date: August 4, 2016
    Inventor: Esa Hussa
  • Patent number: 7498666
    Abstract: The invention relates to an integrated circuit comprising a top package with a first substrate carrying an integrated circuit, and a bottom package with a second substrate carrying at least one die. To increase the clearance between the top package and the bottom package, the invention provides a cavity within the lower surface of the top package substrate such that at least parts of the die are placed within the cavity when the top package and the bottom package are assembled into a package stack.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: March 3, 2009
    Assignee: Nokia Corporation
    Inventor: Esa Hussa
  • Publication number: 20070228542
    Abstract: The invention relates to an integrated circuit comprising a top package with a first substrate carrying an integrated circuit, and a bottom package with a second substrate carrying at least one die. To increase the clearance between the top package and the bottom package, the invention provides a cavity within the lower surface of the top package substrate such that at least parts of the die are placed within the cavity when the top package and the bottom package are assembled into a package stack.
    Type: Application
    Filed: September 27, 2004
    Publication date: October 4, 2007
    Inventor: Esa Hussa
  • Publication number: 20070165388
    Abstract: An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.
    Type: Application
    Filed: March 5, 2007
    Publication date: July 19, 2007
    Inventor: Esa Hussa
  • Patent number: 7233057
    Abstract: The invention relates to an integrated circuit package, in particular an integrated chip size package or an integrated chip scale package, comprising a substrate carrying a die, and connection elements, interconnection elements, connecting pins of said die with said connection elements, and a mold encapsulating said die on said substrate. To increase reliability and to reduce failure due to deformation stress, the invention provides said mold with reduced stiffness at areas located substantially at one of said interconnection elements providing increased flexibility of said package at said areas compared to other areas of said package.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 19, 2007
    Assignee: Nokia Corporation
    Inventor: Esa Hussa
  • Patent number: 7223681
    Abstract: An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: May 29, 2007
    Assignee: Nokia Corporation
    Inventor: Esa Hussa
  • Publication number: 20050263886
    Abstract: The invention relates to an integrated circuit package, in particular an integrated chip size package or an integrated chip scale package, comprising a substrate carrying a die, and connection elements, interconnection elements, connecting pins of said die with said connection elements, and a mold encapsulating said die on said substrate. To increase reliability and to reduce failure due to deformation stress, the invention provides said mold with reduced stiffness at areas located substantially at one of said interconnection elements providing increased flexibility of said package at said areas compared to other areas of said package.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 1, 2005
    Inventor: Esa Hussa
  • Publication number: 20040251544
    Abstract: An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered comers. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.
    Type: Application
    Filed: May 17, 2004
    Publication date: December 16, 2004
    Applicant: Nokia Corporation
    Inventor: Esa Hussa
  • Publication number: 20040227233
    Abstract: An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 18, 2004
    Applicant: Nokia Corporation
    Inventor: Esa Hussa