Patents by Inventor Esakkimuthu DHAKSHINAMOORTHY

Esakkimuthu DHAKSHINAMOORTHY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Performance power optimized full adder
    Patent number: 10613829
    Abstract: A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Manish Srivastava, Esakkimuthu Dhakshinamoorthy, Neha Gupta
  • PERFORMANCE POWER OPTIMIZED FULL ADDER
    Publication number: 20190354347
    Abstract: A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: Manish SRIVASTAVA, Esakkimuthu DHAKSHINAMOORTHY, Neha GUPTA