Patents by Inventor Esfir Natanzon
Esfir Natanzon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9760158Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: GrantFiled: June 6, 2014Date of Patent: September 12, 2017Assignee: Intel CorporationInventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Patent number: 9710043Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.Type: GrantFiled: November 26, 2014Date of Patent: July 18, 2017Assignee: INTEL CORPORATIONInventors: Eliezer Weissmann, Hisham Abu Salah, Efraim Rotem, Guy M. Therien, Nadav Shulman, Esfir Natanzon, Paul S. Diefenbaugh
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Publication number: 20170132007Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.Type: ApplicationFiled: January 23, 2017Publication date: May 11, 2017Inventors: Gadi Haber, Konstantin Kostya Levit-Gurevich, Esfir Natanzon, Boris Ginzburg, Aya Elhanan, Moshe Maury Bach, Igor Breger
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Patent number: 9552207Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.Type: GrantFiled: February 2, 2016Date of Patent: January 24, 2017Assignee: Intel CorporationInventors: Gadi Haber, Konstantin Kostya Levit-Gurevich, Esfir Natanzon, Boris Ginzburg, Aya Elhanan, Moshe Maury Bach, Igor Breger
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Publication number: 20170018051Abstract: A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.Type: ApplicationFiled: September 28, 2016Publication date: January 19, 2017Inventors: Boris Ginzburg, Esfir Natanzon, Ilya Osadchiy, Yoav Zach
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Publication number: 20160154651Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.Type: ApplicationFiled: February 2, 2016Publication date: June 2, 2016Inventors: Gadi Haber, Konstantin Kostya Levit-Gurevich, Esfir Natanzon, Boris Ginzburg, Aya Elhanan, Moshe Maury Bach, Igor Breger
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Publication number: 20160147275Abstract: In one embodiment, a processor includes one or more cores to execute instructions and a power controller coupled to the one or more cores. In turn, the power controller includes a control logic to receive an indication, from one or more sources, of a dynamic change to a guaranteed frequency at which at least one of the one or more cores are to operate, and to determine a final guaranteed frequency at which the processor is to operate for a next window, and to communicate the final guaranteed frequency to at least one entity. Other embodiments are described and claimed.Type: ApplicationFiled: November 26, 2014Publication date: May 26, 2016Inventors: Eliezer Weissmann, Hisham Abu Salah, Efraim Rotem, Guy M. Therien, Nadav Shulman, Esfir Natanzon, Paul S. Diefenbaugh
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Patent number: 9348594Abstract: An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.Type: GrantFiled: December 29, 2011Date of Patent: May 24, 2016Assignee: Intel CorporationInventors: Koichi Yamada, Boris Ginzburg, Wei Li, Ronny Ronen, Esfir Natanzon, Konstantin Levit-Gurevich, Gadi Haber, Alon Naveh, Eliezer Weissmann, Michael Mishaeli
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Publication number: 20160070321Abstract: In one embodiment, a processor includes multiple cores and a power control unit (PCU) coupled to the cores. The PCU has a stress detector to receive a voltage and a temperature at which the processor is operating and calculate lifetime statistical information including effective reliability stress, maintain the lifetime statistical information over multiple boot cycles of a computing system such as personal computer, server computer, tablet computer, smart phone or any other computing platform, control one or more operating parameters of the processor based on the lifetime statistical information, and communicate at least a portion of the lifetime statistical information to a user and/or a management entity via an interface of the processor. Other embodiments are described and claimed.Type: ApplicationFiled: September 10, 2014Publication date: March 10, 2016Inventors: Dorit Shapira, Efraim Rotem, Doron Rajwan, Nadav Shulman, Esfir Natanzon, Nir Rosenzweig
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Patent number: 9250906Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.Type: GrantFiled: August 30, 2015Date of Patent: February 2, 2016Assignee: Intel CorporationInventors: Gadi Haber, Konstantin Kostya Levit-Gurevich, Esfir Natanzon, Boris Ginzburg, Aya Elhanan, Moshe Maury Bach, Igor Breger
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Publication number: 20150377955Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Dorit Shapira, Krishnakanth V. Sistla, Efraim Rotem, Eric Distefano, James G. Hermerding, II, Esfir Natanzon
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Publication number: 20150370567Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.Type: ApplicationFiled: August 30, 2015Publication date: December 24, 2015Inventors: Gadi Haber, Konstantin Kostya Levit-Gurevich, Esfir Natanzon, Boris Ginzburg, Aya Elhanan, Moshe Maury Bach, Igor Breger
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Publication number: 20150355705Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.Type: ApplicationFiled: June 6, 2014Publication date: December 10, 2015Inventors: Eliezer Weissmann, Yoni Aizik, Doron Rajwan, Nir Rosenzweig, Efraim Rotem, Barnes Cooper, Paul S. Diefenbaugh, Guy M. Therien, Michael Mishaeli, Nadav Shulman, Ido Melamed, Niv Tokman, Alexander Gendler, Arik Gihon, Yevgeni Sabin, Hisham Abu Salah, Esfir Natanzon
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Patent number: 9141361Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.Type: GrantFiled: September 30, 2012Date of Patent: September 22, 2015Assignee: Intel CorporationInventors: Gadi Haber, Konstantin Kostya Levit-Gurevich, Esfir Natanzon, Boris Ginzburg, Aya Elhanan, Moshe Maury Bach, Igor Breger
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Publication number: 20140095832Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.Type: ApplicationFiled: September 30, 2012Publication date: April 3, 2014Inventors: Gadi Haber, Konstantin Kostya Levit-Gurevich, Esfir Natanzon, Boris Ginzburg, Aya Elhanan, Moshe Maury Bach, Igor Breger
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Publication number: 20140019723Abstract: An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution.Type: ApplicationFiled: December 28, 2011Publication date: January 16, 2014Inventors: Koichi Yamada, Ronny Ronen, Wei Li, Boris Ginzburg, Gadi Haber, Konstantin Levit-Gurevich, Esfir Natanzon, Alon Naveh, Eliezer Weissmann, Michael Mishaeli
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Publication number: 20130268742Abstract: An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP.Type: ApplicationFiled: December 29, 2011Publication date: October 10, 2013Inventors: Koichi Yamada, Boris Ginzburg, Wei Li, Ronny Ronen, Esfir Natanzon, Konstantin Levit-Gurevich, Gadi Haber, Alon Naveh, Eliezer Weissmann, Michael Mishaeli
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Publication number: 20120236010Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.Type: ApplicationFiled: March 15, 2011Publication date: September 20, 2012Inventors: Boris Ginzburg, Esfir Natanzon, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Yoav Zach, Robert L. Farrell
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Publication number: 20120233439Abstract: Page faults arising in a graphics processing unit may be handled by an operating system running on the central processing unit. In some embodiments, this means that unpinned memory can be used for the graphics processing unit. Using unpinned memory in the graphics processing unit may expand the capabilities of the graphics processing unit in some cases.Type: ApplicationFiled: March 11, 2011Publication date: September 13, 2012Inventors: Boris Ginzburg, Esfir Natanzon, Ilya Osadchiy, Ronny Ronen, Eliezer Weissmann, Yoav Zach, Robert L. Farrell