Patents by Inventor Esin Kutlu Demirlioglu

Esin Kutlu Demirlioglu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9111754
    Abstract: Systems and methods for floating gate structures with high electrostatic discharge performance. In one embodiment, a semiconductor structure includes a floating gate device. The floating gate device includes an embedded diode characterized as having less temperature dependence than a Zener diode. The breakdown voltage of the embedded diode is greater than an operating voltage of an associated integrated circuit and a snapback trigger voltage of the embedded diode is lower than a breakdown voltage of the semiconductor structure.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: August 18, 2015
    Assignee: Vishay-Siliconix
    Inventors: Esin Kutlu Demirlioglu, Min-Yih Luo
  • Patent number: 6091111
    Abstract: A high voltage MOS device includes a P-type substrate having an N-type buried layer formed therein. An N-type epitaxial layer overlies the substrate and a P-type well is formed in the epitaxial layer. A source region is formed in the well such that the source region is directly in contact with the well. No intermediate layer is disposed between the source region and the well. A drain region includes an extended drain region. The extended drain region, which is formed within and in contact with the well, comprises different dopant species and has a maximum dopant concentration of 3.5.times.10.sup.17 cm.sup.-3. A heavily doped main drain region is formed within and in contact with the extended drain region. The source region and extended drain region define a channel region therebetween in the well. An insulator is on a surface of the well over the channel region. A gate is over the insulator.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: July 18, 2000
    Assignee: National Semiconductor Corporation
    Inventors: Esin Kutlu Demirlioglu, Monir H. El-Diwany
  • Patent number: 5994718
    Abstract: A trench refill for a semiconductor device is undertaken by depositing polycrystalline Ge or Ge.sub.x Si.sub.1-x alloy at temperatures as low as 500.degree. C. The structure is then oxidized at for example 700.degree. C. to obtain a cap oxide on the trench refill. This method causes avoidance of (1) void formation, (2) facet formation, and (3) necessity of a second insulator deposition and planarization, meanwhile achieving all these advantages at a low thermal budget.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: November 30, 1999
    Assignee: National Semiconductor Corporation
    Inventor: Esin Kutlu Demirlioglu
  • Patent number: 5893742
    Abstract: A high voltage NMOS device includes an extended drain region formed by implantation of arsenic and phosphorus and a drivein of both the species. The dosage of arsenic is substantially higher than the dosage of phosphorus, so that upon drivein, the slower diffusing arsenic is highly concentrated near the surface of the extended drain region, while the more rapidly diffusing phosphorus provides a gradual gradient of concentration of dopant into the extended drain region.
    Type: Grant
    Filed: September 19, 1996
    Date of Patent: April 13, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Esin Kutlu Demirlioglu, Monir H. El-Diwany