Patents by Inventor Esko Juhani Nieminen

Esko Juhani Nieminen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140173374
    Abstract: Methods and apparatus are described for implementing low-density parity-check codes. These may be used in electronic communications, such as wireless communication systems. A number of processes are implemented for each vector in a plurality of vectors of a coding matrix associated with a low-density parity-check code. These include retrieving, from one or more interleavers, one or more addresses, using the or each retrieved address to retrieve one or more symbols from data and determining a parity-check operation corresponding to a particular said vector using said one or more symbols retrieved from said data. This enables an encoded block to be generated using said data and each of the parity-check operations. It also enables a received code vector to be decoded.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 19, 2014
    Applicant: Broadcom Corporation
    Inventor: Esko Juhani NIEMINEN
  • Patent number: 8446813
    Abstract: Control bits for switches of a butterfly network are directly solved iteratively for each successive functional column of switches to route data values in parallel according to a multiple access scheme through the butterfly network to memory spaces. A memory space address and appended bus index leading into the butterfly network are generated. A linear order bus index and a physical address are determined for a switch having an unsolved control bit. The solved control bits are applied to solve control bits to a next functional column in a linear and an interleaved order by starting from the bus index and physical address. The linear order is moved to the interleaved order by a reduced turbo de-interleaver and the interleaved order is moved to the linear order by a reduced turbo interleaver until solving a sequence of control bits related to the start bus index and the start physical address.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: May 21, 2013
    Assignee: Renesas Mobile Corporation
    Inventor: Esko Juhani Nieminen
  • Patent number: 8397150
    Abstract: A chunk of branch metric computation bits is generated including bits that correspond to transition bits of a possible chunk of transition bits that could have been generated by a state transition of a convolutional encoder of a transmitter. The bits of the chunk of branch metric computation bits are scrambled. A branch metric for the received chunk of soft scrambled code bits is calculated as a function of the scrambled bits of the chunk of branch metric computation bits and the soft scrambled code bits of the received chunk of soft scrambled code bits. The branch metric is indicative of the probability that the received chunk of soft scrambled code bits was originally generated by the convolutional encoder as the chunk of transition bits corresponding to the generated chunk of branch metric computation bits.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 12, 2013
    Assignee: Renesas Mobile Corporation
    Inventors: Esko Juhani Nieminen, Roy Skovgaard Hansen