Abstract: A radio device comprises a radio transceiver, a resonator, a temperature measurement unit, a frequency synthesiser and a processing system. A temperature signal from the temperature measurement unit, representative of a measured temperature of the resonator, is used to determine an estimated frequency offset for the resonator at the measured temperature using a model stored in a memory of the processing system that relates frequency offset to temperature. A periodic signal from the resonator is provided to the frequency synthesizer, which, in dependence on the estimated frequency offset, is used to generate a periodic local signal. The radio transceiver receives a radio signal comprising a periodic component at a received signal frequency. An error value representative of a difference between the received signal frequency and a frequency of the periodic local signal is determined and used to update one or more parameters of the model stored in the memory.

Abstract: A sorting deck for paper, board, or pulp rolls has a plane (1) for transporting the rolls and controllable stops (2) for holding the rolls in place and releasing them. The stops (2) are positioned to form at least one line (3) in placed consecutively in the longitudinal direction (4) of the plane (1), and at least one row (5), in which the stops (2) are positioned adjacently to each other along the lateral direction (6) of the plane (1). At least some of the stops (2) are a collector (41) and a feeder (42), both of which can be moved freely between the hold and release positions, so that the travel of the rolls over the stop (2) can be optionally prevented, freely permitted, or permitted one roll at a time. The same sorting deck can be used to handle rolls of different widths.

Abstract: A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.

Abstract: A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks in accordance with a multiple access rule to enable parallel access to the memory bank, without memory access conflict, for one of a linear order and an interleaved order. The method and apparatus is particularly advantageous for use in turbo decoding.

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract: A first grouping of memory space addresses is generated for systematic bits of a received codeword; a second grouping of memory space addresses is generated for a first set of coding bits of the received codeword, wherein the first set of coding bits comprises an ascending order; and a third grouping of memory space addresses is generated for a second set of coding bits of the received codeword, wherein the second set of coding bits comprises an interleaved order. A sub-codeword of the received codeword is decoded in parallel by accessing the first set of coding bits using the addresses in the second grouping of memory spaces. In turn, another sub-codeword of the received codeword is decoded in parallel by accessing the second set of coding bits using the addresses in the third grouping of memory spaces. Apparatus and a memory storing a computer program are also detailed.

Abstract: A sorting deck for paper, board, or pulp rolls has a plane (1) for transporting the rolls and controllable stops (2) for holding the rolls in place and releasing them. The stops (2) are positioned to form at least one line (3) in placed consecutively in the longitudinal direction (4) of the plane (1), and at least one row (5), in which the stops (2) are positioned adjacently to each other along the lateral direction (6) of the plane (1). At least some of the stops (2) are a collector (41) and a feeder (42), both of which can be moved freely between the hold and release positions, so that the travel of the rolls over the stop (2) can be optionally prevented, freely permitted, or permitted one roll at a time. The same sorting deck can be used to handle rolls of different widths.

Abstract: A memory bank has a plurality of memories. In an embodiment, a forward unit applies logical memory addresses to the memory bank in a forward twofold access order, a backward unit applies logical memory addresses to the memory bank in a backward twofold access order, and a half butterfly network (at least half, and barrel shifters in 8-tuple embodiments) is disposed between the memory bank and the forward unit and the backward unit. A set of control signals is generated which are applied to the half or more butterfly network (and to the barrel shifters where present) so as to access the memory bank with an n-tuple parallelism in a linear order in a first instance, and a quadratic polynomial order in a second instance, where n=2, 4, 8, 16, 32, . . . . This access is for any n-tuple of the logical addresses, and is without memory access conflict. In this manner memory access may be controlled data decoding.

Abstract: A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks in accordance with a multiple access rule to enable parallel access to the memory bank, without memory access conflict, for one of a linear order and an interleaved order. The method and apparatus is particularly advantageous for use in turbo decoding.

Abstract: In one aspect this invention provides a method to operate a decoder, and a decoder that operates in accordance with the method. The method includes monitoring, during operation of the decoder on a signal received from a channel, the value of at least one extrinsic value; and based on the monitored at least one value, determining whether the signal comprises a valid code word or comprises only noise. In a preferred, but non-limiting embodiment, the decoder comprises one of a LogMap or a MaxLogMap turbo decoder, and the decoder forms a part of a baseband section of a wideband code division multiple access (WCDMA) user equipment. During the process of decoding rounds the absolute values of extrinsic values tend to increase, provided that the input signal contains a valid code word, as opposed to when the input signal contains only noise, and where determining accurately distinguishes a valid code word from noise, and may also obtain information that is indicative of the quality of the decoding process.

Abstract: An arrangement and method for decoding a convolutionally encoded codeword employs a window sliding over the codeword. Path metrics are computed simultaneously forwards and backwards in the sliding window. A decoding result is computed in a synthesis unit on the basis of the path metrics. The sliding window is divided into four parts. Path metrics are computed in the forward direction in the first part of the sliding window and stored in a four-part memory. Path metrics are computed in the backward direction in two other parts of the sliding window in such a way that the input of the computation units comes from the four-part memory; the computed metrics are applied to the synthesis unit; and a decoding result is computed.

Abstract: The invention relates to trellis code decoder. The decoder comprises a path metrics calculation unit for calculating path metrics over at least two trellis columns in a trellis, and a memory for storing path metrics of the trellis. The decoder further comprises an input multiplexer connected between the read interface of the memory and the input interface of the path metrics calculation unit, and an output multiplexer connected between the output interface of the path metrics calculation unit and the write interface of the memory. The decoder further comprises a control for controlling configuration of the input multiplexer and configuration of the output multiplexer on the basis of states of the trellis, which state of the trellis defines the way the old path metrics and the new path metrics relate to each other, whereby internal configuration of the path metrics calculation unit remains the same for different code constraint lengths.

Abstract: An arrangement and method for decoding a convolutionally encoded codeword employs a window sliding over the codeword. Path metrics are computed simultaneously forwards and backwards in the sliding window. A decoding result is computed in a synthesis unit on the basis of the path metrics. The sliding window is divided into four parts. Path metrics are computed in the forward direction in the first part of the sliding window and stored in a four-part memory. Path metrics are computed in the backward direction in two other parts of the sliding window in such a way that the input of the computation units comes from the fourpart memory; the computed metrics are applied to the synthesis unit; and a decoding result is computed.

Abstract: The invention relates to a method and an apparatus for producing path metrics in a trellis. The trellis phase nodes that have the common nodes of the preceding trellis phase through the allowed state transitions determined by the code are defined as basic group nodes. Then path metrics corresponding to the code are produced, and in each basic group winner information on the winner path and path metric information on the rejected paths is stored in a memory in respect of only one node. Finally the signal is re-processed in the opposite direction trellis phase by trellis phase starting from the path metrics produced last by producing the path metrics of the preceding trellis phase basic group by basic group using the path metrics of the one node of the basic group of the present trellis phase and the winner information and path metric information stored in the memory.

Abstract: In one aspect this invention provides a method to operate a decoder, and a decoder that operates in accordance with the method. The method includes monitoring, during operation of the decoder on a signal received from a channel, the value of at least one extrinsic value; and based on the monitored at least one value, determining whether the signal comprises a valid code word or comprises only noise. In a preferred, but non-limiting embodiment, the decoder comprises one of a LogMap or a MaxLogMap turbo decoder, and the decoder forms a part of a baseband section of a wideband code division multiple access (WCDMA) user equipment. During the process of decoding rounds the absolute values of extrinsic values tend to increase, provided that the input signal contains a valid code word, as opposed to when the input signal contains only noise, and where determining accurately distinguishes a valid code word from noise, and may also obtain information that is indicative of the quality of the decoding process.

Abstract: The invention relates to a method and arrangement for decoding a turbo coded code word comprising termination bits. The received code word samples are applied to a decoder in a sequence required by the code structure. Termination samples are grouped according to different components of the code word, code interleavers are extended such that the extension part comprises addresses of the systematic termination samples. The address of the ascending order is formed after the actual code word samples such that the addresses of the extension part are addresses of the systematic termination samples corresponding to the termination samples of one or more parities of ascending order and those of the extrinsic weight coefficients related to said systematic termination samples. Decoding is executed by using the extended, ascending address formation and one or more extended interleavers.

Abstract: The invention relates to trellis code decoder. The decoder comprises a path metrics calculation unit for calculating path metrics over at least two trellis columns in a trellis, and a memory for storing path metrics of the trellis. The decoder further comprises an input multiplexer connected between the read interface of the memory and the input interface of the path metrics calculation unit, and an output multiplexer connected between the output interface of the path metrics calculation unit and the write interface of the memory. The decoder further comprises a control for controlling configuration of the input multiplexer and configuration of the output multiplexer on the basis of states of the trellis, which state of the trellis defines the way the old path metrics and the new path metrics relate to each other, whereby internal configuration of the path metrics calculation unit remains the same for different code constraint lengths.

Abstract: The invention relates to three different methods for updating a linear feedback shift register of a code generator, and code generators applying the methods. In the basic method a Galois-type linear feedback shift register of a code generator is updated to a target state which is at a known offset from a unit state. The basic method comprises the following: (302) generating a binary offset number illustrating the offset; (304) generating a counter showing the number of bits in the binary offset number; (306) initializing a temporary state with the unit state; (308) iterating as long as the counter value is higher than zero: (310) multiplying the temporary state by itself by applying a Galois Field multiplication; (312) shifting the temporary state one state forward from the current temporary state if the value of the bit shown by the counter is one; and (314) decrementing the counter value by one; (316) in the end, when the counter has reached the value zero, setting the temporary state as the target state.

Abstract: The invention relates to a method and an apparatus for producing path metrics in a trellis. The trellis phase nodes that have the common nodes of the preceding trellis phase through the allowed state transitions determined by the code are defined as basic group nodes. Then path metrics corresponding to the code are produced, and in each basic group winner information on the winner path and path metric information on the rejected paths is stored in a memory in respect of only one node. Finally the signal is re-processed in the opposite direction trellis phase by trellis phase starting from the path metrics produced last by producing the path metrics of the preceding trellis phase basic group by basic group using the path metrics of the one node of the basic group of the present trellis phase and the winner information and path metric information stored in the memory.

Abstract: The present invention relates to a method and apparatus for forming a group of rolls of at least two rolls of paper, board or cellulosic material web, said method comprising the steps of separating apart from each other the rolls (3, 4, 5, 6, 7) of a roll set received from said slitter-winder (1), and combining desired rolls (3, 4, 5) of the roll set into a multi-roll pack. At least one of the desired rolls (3, 4, 5) to be included in the multi-roll pack is taken apart from the other rolls (6, 7) of the roll set resting on a conveyor (8, 9) and is moved to a waiting station (10) and is then moved back from the waiting station (10) onto the conveyor (9) in a manner allowing the desired rolls (3, 4, 5) of the multi-roll pack to be sorted into a desired order having the adjacent ends of the rolls facing each other.