Patents by Inventor Esko O. Mikkola

Esko O. Mikkola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10082535
    Abstract: A test structure includes a dedicated addressing circuit that allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test structure may be configured for wafer, die or package-level testing. The test structure may be integrated on a common die with the test devices in a single package, provided on separate die in a common package, separately packaged chips or in the form of a collection of standard die configured as the test structure. If on separate die, the test and addressing circuitry is fabricated from a more mature fabrication process than that being characterized for the devices under test. The processes being characterized may be unqualified whereas the test circuitry may be fabricated with different and more mature or qualified processes.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 25, 2018
    Assignee: Ridgetop Group, Inc.
    Inventors: Esko O. Mikkola, Hans A. R. Manhaeve
  • Publication number: 20160161548
    Abstract: A test structure includes a dedicated addressing circuit that allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test structure may be configured for wafer, die or package-level testing. The test structure may be integrated on a common die with the test devices in a single package, provided on separate die in a common package, separately packaged chips or in the form of a collection of standard die configured as the test structure. If on separate die, the test and addressing circuitry is fabricated from a more mature fabrication process than that being characterized for the devices under test. The processes being characterized may be unqualified whereas the test circuitry may be fabricated with different and more mature or qualified processes.
    Type: Application
    Filed: January 28, 2016
    Publication date: June 9, 2016
    Inventors: Esko O. Mikkola, Hans A.R. Manhaeve
  • Patent number: 9275187
    Abstract: A test chip, system and method for testing large numbers of test devices on a single test chip decreases the time and complexity required to characterize the variation and reliability of the IC fabrication process. A remotely configurable test chip can be programmed with varying bias conditions for testing of process variation or numerous failure modes on large sample sizes. An on-chip addressing technique allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test chip may be configured for wafer, die or package-level testing.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: March 1, 2016
    Assignee: Ridgetop Group, Inc.
    Inventor: Esko O. Mikkola
  • Publication number: 20120245879
    Abstract: A test chip, system and method for testing large numbers of test devices on a single test chip decreases the time and complexity required to characterize the variation and reliability of the IC fabrication process. A remotely configurable test chip can be programmed with varying bias conditions for testing of process variation or numerous failure modes on large sample sizes. An on-chip addressing technique allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test chip may be configured for wafer, die or package-level testing.
    Type: Application
    Filed: March 19, 2012
    Publication date: September 27, 2012
    Inventor: Esko O. Mikkola