Abstract: A power gated variable hop cycle beam laydown (700) manifests itself as first cells (C, D) supported by a first hop cycle, second cells (G, H) supported by a second hop cycle, and transition cells (E, F) supported by a transition hop cycle. The transition hop cycle uses power gating to transition the laydown (700) from cells (C, D) operating at the first hop cycle to cells (G, H) operating at the second hop cycle. To this end, the transition hop cycle power gates its downlink beam for a portion of time needed to reduce interference between nearby (e.g., adjacent) cells.

Abstract: A downlink beam frame signal processing system (100) for a communication satellite includes a packet switch (608) that routes self addressed uplink data to a memory (804). The memory (804) stores queues for at least a first and a second downlink beam hop locations (302, 304). The processing system (100) also includes a power amplifier (108) that amplifies a waveform formed using the uplink data. A power gating circuit (1200) coupled to the power amplifier (108) includes a power gate input (1216) responsive to a power gating signal to remove RF power from at least a portion of the waveform before transmission.

Abstract: A frame signal (100) for communicating payloads (104, 110) of data includes a first payload field (104) and a first header field (102) with a first frame type indicator (120). The frame signal (100) also includes a second payload field (110) and a second header field (108) smaller than the first header field (102) that includes a second frame type indicator (128). The first payload field (104), first header field (102), second payload field (110), and the second header field (108) are encapsulated in a single frame (100) to provide multiple payload delivery with reduced overhead compared to individually transmitted single payload frames.

Abstract: A power gating module (200) for a downlink beam frame signal (402) includes a power amplifier (210) for amplifying for transmission frame signals that include at least a first header signal (418), a first payload signal (420), a second header signal (424), and a second payload signal (426). The power gating module (200) further includes a power gating circuit (300) coupled to the power amplifier (210). The power gating circuit (300) includes a power gate input (318) and is responsive to a power gating signal to remove power from at least one of the first header signal (418) and first payload signal (420) in combination, and the second header signal (424) and second payload signal (426) in combination before amplification by the power amplifier (210).