Abstract: A semiconductor memory circuit having a controller by means of which the semiconductor memory circuit can be switched into a standby mode with a reduced power requirement, comprises an analog subcircuit having a power input and a signal output and is characterized by the fact that a switching device for feeding electrical power is connected to the power input and the controller is connected to the switching device in such a way that the switching device can be driven by the controller in such a way that the switching device, in the standby mode, supplies the analog subcircuit with electrical power during a first periodically repeated time duration and does not supply it with electrical power during a second periodically repeated time duration.

Abstract: A semiconductor memory circuit having a controller by means of which the semiconductor memory circuit can be switched into a standby mode with a reduced power requirement, comprises an analog subcircuit having a power input and a signal output and is characterized by the fact that a switching device for feeding electrical power is connected to the power input and the controller is connected to the switching device in such a way that the switching device can be driven by the controller in such a way that the switching device, in the standby mode, supplies the analog subcircuit with electrical power during a first periodically repeated time duration and does not supply it with electrical power during a second periodically repeated time duration.

Abstract: The invention relates to an evaluation circuit for reading out the information stored in a memory cell, the current (read-out current) carried on a bit line (3) being assessed, the evaluation circuit (10) comprising a bit line decoder (2) and a precharge and converter circuit (4). In order to reduce the read-out duration particularly in the case of large scale integrated memory cells (1), a current source (6) is provided, which increases the read-out current (Imeas) by an offset current (Ioff).

Abstract: To reduce the total bit-line capacitance in a semiconductor memory arrangement, it is proposed that the semiconductor memory arrangement be so divided into a plurality of memory blocks (9) that each memory block (9) has a corresponding data bus and a group of sense amplifiers (1) connected to this data bus (2) associated with it. In this way it is possible for the bus-line capacitance (CB), which contributes to the total bit-line capacitance, to be reduced because the bus-line capacitance then depends simply on the length of a memory sector (6).

Abstract: The object is to discharge a first capacitor from a high voltage to a low voltage. To this end, the one electrode of the first capacitor is linked with the one electrode of a second capacitor via a FET path. The other two electrodes of the two capacitors are connected to reference potential. A voltage source with its internal resistance is connected in parallel to the second capacitor. A discharge path leads from the one electrode of the first capacitor from the paths of two FET and a protective resistor to the reference potential. A current path leads from the one electrode of the second capacitor to the reference potential via the paths of two additional FET. A control unit switches on the discharge path. Once the voltage of the first capacity has decreased to the required lower value, the discharge path is blocked while a holding path is opened.

Abstract: The object is to discharge a first capacitor from a high voltage to a low voltage. To this end, the one electrode of the first capacitor is linked with the one electrode of a second capacitor via a FET path. The other two electrodes of the two capacitors are connected to reference potential. A voltage source with its internal resistance is connected in parallel to the second capacitor. A discharge path leads from the one electrode of the first capacitor from the paths of two FET and a protective resistor to the reference potential. A current path leads from the one electrode of the second capacitor to the reference potential via the paths of two additional FET. A control unit switches on the discharge path. Once the voltage of the first capacity has decreased to the required lower value, the discharge path is blocked while a holding path is opened.

Abstract: To reduce the total bit-line capacitance in a semiconductor memory arrangement, it is proposed that the semiconductor memory arrangement be so divided into a plurality of memory blocks (9) that each memory block (9) has a corresponding data bus and a group of sense amplifiers (1) connected to this data bus (2) associated with it. In this way it is possible for the bus-line capacitance (CB), which contributes to the total bit-line capacitance, to be reduced because the bus-line capacitance then depends simply on the length of a memory sector (6).

Abstract: A sense amplifier for nonvolatile memories includes a first line path (precharging path) having a first transistor and a third transistor connected in series with the bit line for a memory cell that is to be read. The sense amplifier also includes a second line path (reading path), running parallel to the first line path, in which a transistor diode and a fourth transistor are connected in series with the bit line. The gates of the third transistor and of the fourth transistor are at the same potential, in particular, are connected to one another.

Abstract: The invention relates to an evaluation circuit for reading out the information stored in a memory cell, the current (read-out current) carried on a bit line (3) being assessed, the evaluation circuit (10) comprising a bit line decoder (2) and a precharge and converter circuit (4). In order to reduce the read-out duration particularly in the case of large scale integrated memory cells (1), a current source (6) is provided, which increases the read-out current (Imeas) by an offset current (Ioff).

Abstract: A sense amplifier for nonvolatile memories includes a first line path (precharging path) having a first transistor and a third transistor connected in series with the bit line for a memory cell that is to be read. The sense amplifier also includes a second line path (reading path), running parallel to the first line path, in which a transistor diode and a fourth transistor are connected in series with the bit line. The gates of the third transistor and of the fourth transistor are at the same potential, in particular, are connected to one another.