Patents by Inventor Eswararao Potladhurthi
Eswararao Potladhurthi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10783956Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: January 9, 2019Date of Patent: September 22, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Patent number: 10783958Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: April 19, 2019Date of Patent: September 22, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Patent number: 10522217Abstract: Disclosed is a chip with a memory array and at least one positive voltage boost circuit, which provides positive voltage boost pulses to the sources of pull-up transistors in the memory cells of the array during write operations to store data values in those memory cells and, more specifically, provides positive voltage boost pulses substantially concurrently with wordline deactivation during the write operations to ensure that the data is stored. Application of such pulses to different columns can be performed using different positive voltage boost circuits to minimize power consumption. Also disclosed are a memory array operating method that employs a positive voltage boost circuit and a chip manufacturing method, wherein post-manufacture testing is performed to identify chips having memory arrays that would benefit from positive voltage boost pulses and positive voltage boost circuits are attached to those identified chips and operably connected to the memory arrays.Type: GrantFiled: August 8, 2018Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Venkatraghavan Bringivijayaraghavan, Eswararao Potladhurthi, George M. Braceras
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Publication number: 20190304536Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: April 19, 2019Publication date: October 3, 2019Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Patent number: 10319431Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: October 31, 2017Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Publication number: 20190147946Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: January 9, 2019Publication date: May 16, 2019Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Patent number: 10217510Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: October 31, 2017Date of Patent: February 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Patent number: 9984742Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: April 13, 2016Date of Patent: May 29, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Publication number: 20180130522Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: October 31, 2017Publication date: May 10, 2018Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Publication number: 20180068717Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Patent number: 9847119Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: September 15, 2016Date of Patent: December 19, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Publication number: 20170004876Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: September 15, 2016Publication date: January 5, 2017Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Patent number: 9496025Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: GrantFiled: January 12, 2015Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
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Publication number: 20160232966Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: April 13, 2016Publication date: August 11, 2016Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Publication number: 20160203857Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.Type: ApplicationFiled: January 12, 2015Publication date: July 14, 2016Inventors: Dinesh CHANDRA, Eswararao POTLADHURTHI, Dhani Reddy Sreenivasula REDDY, Krishnan S. RENGARAJAN
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Publication number: 20110133809Abstract: A semiconductor device includes first and second signal lines; a sense amplifier amplifying potential difference occurring in the first and second signal lines; a cancel charge generator circuit producing cancel charge that corresponds to offset voltage in the sense amplifier; a cancel charge storage circuit storing the cancel charge; and a cancel charge feed circuit feeding the cancel charge that has been stored in the cancel charge storage circuit to the first and second signal lines to cancel the offset voltage.Type: ApplicationFiled: December 3, 2009Publication date: June 9, 2011Applicant: Elpida Memory, Inc.Inventors: Ankur Goel, Eswararao Potladhurthi