Patents by Inventor Etai Adar
Etai Adar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120089985Abstract: Sampled instruction address registers are shared among multiple threads executing on a plurality of processor cores. Each of a plurality of sampled instruction address registers are assigned to a particular thread running for an application on the plurality of processor cores. Each of the sampled instruction address registers are configured by storing in each of the sampled instruction address registers a thread identification of the particular thread in a thread identification field and a processor identification of a particular processor on which the particular thread is running in a processor identification field.Type: ApplicationFiled: October 12, 2010Publication date: April 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Russell D. Hoover, Srinivasan Ramani, Eric F. Robinson, Thuong Q. Truong
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Publication number: 20120089979Abstract: A number of hypervisor register fields are set to specify which processor cores are allowed to generate a number of performance events for a particular thread group. A plurality of threads for an application running in the computing environment to a plurality of thread groups are configured by a plurality of thread group fields in a plurality of control registers. A number of counter sets are allowed to count a number of thread group events originating from one of a shared resource and a shared cache are specified by a number of additional hypervisor register fields.Type: ApplicationFiled: October 8, 2010Publication date: April 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Srinivasan Ramani, Eric F. Robinson, Thuong Q. Truong
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Publication number: 20120089984Abstract: Counter registers are shared among multiple threads executing on multiple processor cores. An event within the processor core is selected. A multiplexer in front of each of a number of counters is configured to route the event to a counter. A number of counters are assigned for the event to each of a plurality of threads running for a plurality of applications on a plurality of processor cores, wherein each of the counters includes a thread identifier in the interrupt thread identification field and a processor identifier in the processor identification field. The number of counters is configured to have a number of interrupt thread identification fields and a number of processor identification fields to identify a thread that will receive a number of interrupts.Type: ApplicationFiled: October 8, 2010Publication date: April 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Srinivasan Ramani, Eric F. Robinson, Thuong Q. Truong
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Patent number: 8024597Abstract: The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violations in device under test designs comprising two different clock domains where the fast clock rate is an integer multiple of the slow clock rate by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainty of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.Type: GrantFiled: February 21, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Etai Adar, Ilya Granovsky, Efrat Greenberg, Itay Poleg
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Patent number: 7827325Abstract: A mechanism for speculative packet transmission including a credit-based flow control interconnect device to initiate speculative transmission of a Transaction Layer Packet if the number of available flow control (FC) credits is insufficient for completing the transmission. The sending device initiates a speculative transmission of packets to the receiving device even though the packet for transmission requires a number of FC credits greater than the available FC credits. If the additional FC credits required to complete the packet transmission become available to the sending device before the transmission is completed, the packets are then fully transmitted by the sending device. Otherwise, if the additional FC credits required do not become available prior to completion of the transmission, then the sending device aborts the transmission without utilization of the FC credits. The sending device may initiate speculative packet transmission only if a particular minimal amount of FC credits is available.Type: GrantFiled: October 31, 2007Date of Patent: November 2, 2010Assignee: International Business Machines CorporationInventors: Etai Adar, Ilya Granovsky, Zorik Machulsky, Paul J. Mattos
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Publication number: 20100226420Abstract: For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.Type: ApplicationFiled: March 4, 2009Publication date: September 9, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Michael Bar-Joshua, David Stauffer
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Patent number: 7747803Abstract: Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.Type: GrantFiled: November 28, 2007Date of Patent: June 29, 2010Assignee: International Business Machines CorporationInventors: Etai Adar, Michael Bar-Joshua, Atar Peyser, Shaul Yifrach
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Patent number: 7734854Abstract: Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.Type: GrantFiled: January 4, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Etai Adar, Michael Bar-Joshua, Ilya Granovsky, Shaul Yifrach
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Publication number: 20090217075Abstract: The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violation in device under test designs comprising two different clock domains where the fast clock is an integer multiple of the slow clock by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainly of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.Type: ApplicationFiled: February 21, 2008Publication date: August 27, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Ilya Granovsky, Efrat Greenberg, Itay Poleg
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Publication number: 20090187683Abstract: A communications apparatus uses at least one logical communications link that comprises a plurality of lanes within a computerized hardware device. A data transfer monitor is connected to the logical communications link and measures the real-time data transfer bandwidth of the logical communications link. In addition, a link management unit or link width control unit (comparator) is connected to the lanes and to the data transfer monitor and continually compares the real-time data transfer bandwidth to a predetermined data transfer bandwidth standard. If the real-time data transfer bandwidth is below the predetermined data transfer bandwidth standard, the link management unit is adapted to perform up-configuring of the logical communications link by activating additional lanes up to a maximum number of lanes making up the logical communications link.Type: ApplicationFiled: January 22, 2008Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Michael Bar-Joshua, Ilya Granovsky, Shaul Yifrach
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Publication number: 20090185487Abstract: Embodiments herein provide a transaction level mechanism that ensures that the links are operational right in time for the data flow, so that the data flow will not be impacted by delays associated with link recovery into the operational state. The path has links that have the ability to be in an inactive mode or an active mode. The embodiments herein transmit an “activation transmission” over the path to turn on the links within the path, before sending a data transfer (comprising packetized data) to turn on (wake up) the inactive links within the path, so that the actual data transfer does not experience any such start-up or wake-up delays.Type: ApplicationFiled: January 22, 2008Publication date: July 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Michael Bar-Joshua, Ilya Granovsky, Shaul Yifrach
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Patent number: 7562168Abstract: Optimization of a use of memory buffers of a device connected to a physical link including virtual channels (VCs) while sustaining bandwidth for communication between the device and another entity, by determining an initial allocation of memory buffers of each VC. Further, the optimization is accomplished by determining whether a next VC is active or inactive. If the VC is determined to be inactive, a number of memory buffers initially allocated to the inactive channel is determined, and the memory buffers are re-allocated between the active VCs.Type: GrantFiled: May 29, 2008Date of Patent: July 14, 2009Assignee: International Business Machines CorporationInventors: Shaul Yifrach, Ilya Gransovky, Etai Adar, Giora Biran
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Publication number: 20090177822Abstract: Some embodiments include, for example, devices, systems, and methods of handling transactions. In some demonstrative embodiments, an apparatus to handle transactions in a computing system may include a master unit to arbitrate between read and write requests to be issued over a request bus according to at least first and second arbitration schemes. A first ratio between read and write requests issued by the master unit according to the first arbitration scheme may be different from a second ratio between read and write requests issued by the master unit according to the second arbitration scheme.Type: ApplicationFiled: January 4, 2008Publication date: July 9, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Michael Bar-Joshua, Ilya Granovsky, Shaul Yifrach
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Publication number: 20090138641Abstract: Device, system, and method of handling delayed transactions. For example, an apparatus to handle delayed transactions in a computing system includes: a slave unit adapted to pseudo-randomly reject a request received from a master unit.Type: ApplicationFiled: November 28, 2007Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Etai Adar, Michael Bar-Joshua, Atar Peyser, Shaul Yifrach
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Publication number: 20090113082Abstract: Device, system and method of speculative packet transmission. For example, an apparatus for speculative packet transmission includes: a credit-based flow control interconnect device to initiate speculative transmission of a Transaction Layer Packet if a number of available flow control credits is insufficient for completing the transmission.Type: ApplicationFiled: October 31, 2007Publication date: April 30, 2009Inventors: Etai Adar, Ilya Granovsky, Zorik Machulsky, Paul J. Mattos
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Patent number: 6611211Abstract: A method for encoding a data mask that consists of a given total number of bits and includes a selected group of contiguous bits within the total number, the selected group having a left end and a right end. The method includes dividing the data mask into a plurality of segments, and representing the segments by respective segment codes, each code indicating whether the bits in the respective segment fall entirely outside the selected group, entirely within the selected group, or include the left end or the right end of the group. The segment codes are combined so as to generate a mask code, which can be decoded to reconstruct the data mask.Type: GrantFiled: May 4, 2001Date of Patent: August 26, 2003Assignee: International Business Machines CorporationInventors: Dan Ramon, Gil Walzer, Etai Adar
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Publication number: 20020166041Abstract: A method for encoding a data mask that consists of a given total number of bits and includes a selected group of contiguous bits within the total number, the selected group having a left end and a right end. The method includes dividing the data mask into a plurality of segments, and representing the segments by respective segment codes, each code indicating whether the bits in the respective segment fall entirely outside the selected group, entirely within the selected group, or include the left end or the right end of the group. The segment codes are combined so as to generate a mask code, which can be decoded to reconstruct the data mask.Type: ApplicationFiled: May 4, 2001Publication date: November 7, 2002Applicant: International Business Machines CorporationInventors: Dan Ramon, Gil Walzer, Etai Adar
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Patent number: 6021483Abstract: To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.Type: GrantFiled: March 17, 1998Date of Patent: February 1, 2000Assignee: International Business Machines CorporationInventors: Etai Adar, Ophir Nadir, Yehuda Peled