Patents by Inventor Etan Shacham
Etan Shacham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10446498Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.Type: GrantFiled: August 14, 2017Date of Patent: October 15, 2019Assignee: Fairchild Semiconductor CorporationInventors: John Constantino, Timwah Luk, Ahmad Ashrafzadeh, Robert L. Krause, Etan Shacham, Maria Clemens Ypil Quinones, Janusz Bryzek, Chung-Lin Wu
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Publication number: 20170373008Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.Type: ApplicationFiled: August 14, 2017Publication date: December 28, 2017Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: John CONSTANTINO, Timwah LUK, Ahmad ASHRAFZADEH, Robert L. KRAUSE, Etan SHACHAM, Maria Clemens Ypil QUINONES, Janusz BRYZEK, Chung-Lin WU
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Patent number: 9735112Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.Type: GrantFiled: January 9, 2015Date of Patent: August 15, 2017Assignee: Fairchild Semiconductor CorporationInventors: John Constantino, Timwah Luk, Ahmad Ashrafzadeh, Robert L. Krause, Etan Shacham, Maria Clemens Ypil Quinones, Janusz Bryzek, Chung-Lin Wu
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Publication number: 20150200162Abstract: In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.Type: ApplicationFiled: January 9, 2015Publication date: July 16, 2015Inventors: John CONSTANTINO, Timwah LUK, Ahmad ASHRAFZADEH, Robert L. KRAUSE, Etan SHACHAM, Maria Clemens Ypil QUINONES, Janusz BRYZEK, Chung-Lin WU
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Patent number: 7468314Abstract: A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxial layers support the blocking voltage of the diode, and each of the multiple epitaxial layers supports a substantial portion of the blocking voltage. Optimization of the thickness and dopant concentrations of at least the top two epitaxial layers results in reduced capacitance and switching losses, while keeping effects on forward voltage and on-resistance low. Alternatively, the SBD includes a continuously graded N-type doped region whose doping varies from a lighter dopant concentration at the top of the region to a heavier dopant concentration at the bottom.Type: GrantFiled: July 10, 2006Date of Patent: December 23, 2008Assignee: Fairchild Semiconductor CorporationInventors: Praveeen M. Shenoy, Etan Shacham
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Publication number: 20070015308Abstract: A SiC Schottky barrier diode (SBD) is provided having a substrate and two or more epitaxial layers, including at least a thin, lightly doped N-type top epitaxial layer, and an N-type epitaxial layer on which the topmost epitaxial layer is disposed. Multiple epitaxial layers support the blocking voltage of the diode, and each of the multiple epitaxial layers supports a substantial portion of the blocking voltage. Optimization of the thickness and dopant concentrations of at least the top two epitaxial layers results in reduced capacitance and switching losses, while keeping effects on forward voltage and on-resistance low. Alternatively, the SBD includes a continuously graded N-type doped region whose doping varies from a lighter dopant concentration at the top of the region to a heavier dopant concentration at the bottom.Type: ApplicationFiled: July 10, 2006Publication date: January 18, 2007Inventors: Praveen Shenoy, Etan Shacham
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Patent number: 6813209Abstract: A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.Type: GrantFiled: October 14, 2003Date of Patent: November 2, 2004Assignee: Fairchild Semiconductor CorporationInventors: Ethan A. Crain, Karl Rapp, Etan Shacham
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Publication number: 20040136255Abstract: A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.Type: ApplicationFiled: October 14, 2003Publication date: July 15, 2004Inventors: Ethan A. Crain, Karl Rapp, Etan Shacham
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Patent number: 6365449Abstract: In accordance with an embodiment of the present invention, a method of forming a memory cell includes: forming a floating gate over a first portion of a silicon body region, the floating gate being insulated from the underlying first portion of the body region; forming a second layer polysilicon over the floating gate and a second portion of the body region, the second layer polysilicon being insulated from the underlying floating gate and the second portion of the body region; and forming a masking layer over the second layer polysilicon, the masking layer having a width along a first dimension parallel to the surface of the body region such that the masking layer extends over an entire width of the floating gate along the first dimension but does not extend beyond edges of steps of the second layer polysilicon formed due to the presence of the floating gate. Among many other advantages, such method provides a means of accurately controlling the cell channel length.Type: GrantFiled: September 8, 2000Date of Patent: April 2, 2002Assignee: Fairchild Semiconductor CorporationInventors: Max C. Kuo, Etan Shacham
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Patent number: 6033960Abstract: A P-channel MOS device having an elevated breakdown voltage is created without increasing device size or requiring additional fabrication steps. During the P-field implant step, P type dopant is implanted into regions of the silicon expected to lie along the silicon-silicon dioxide interface after silicon dioxide growth.Type: GrantFiled: January 13, 1998Date of Patent: March 7, 2000Assignee: National Semiconductor CorporationInventor: Etan Shacham
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Patent number: 5661060Abstract: A Flash EEPROM memory array and method for making the same is provided. The memory array has rectangularly shaped field oxide regions. A field oxide layer is grown on a substrate having p-wells. The field oxide layer is selectively etched to provide the resulting field oxide regions. Subsequent method steps provide tunnel oxide regions, floating gates oxide-nitride-oxide layers, bit lines, oxide spacers and word lines, word line to metal dielectric, contacts, metal and passivation.Type: GrantFiled: December 28, 1994Date of Patent: August 26, 1997Assignee: National Semiconductor CorporationInventors: Manzur Gill, Etan Shacham
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Patent number: 5512504Abstract: A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.Type: GrantFiled: January 9, 1995Date of Patent: April 30, 1996Assignee: National Semiconductor CorporationInventors: Graham Wolstenholme, Albert Bergemont, Etan Shacham
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Patent number: 5422844Abstract: A nonvolatile semiconductor memory, which includes an array of programmable transistor cells, such as EPROM or EEPROM cells, provides electrical isolation without the use of field oxide islands. The cells are arranged in X number of rows and Y number of columns with the cells in at least two of the rows being designated as select cells and the remaining cells being designated as memory cells. Control circuitry is provided for causing the select cells to supply programming voltages to selected ones of the memory cells. Alternate ones of the select cells are formed as implanted-channel select cells to provide electrical isolation for adjacent select cells which remain in the low threshold (active) state. The implanted-channel select cells are formed by implanting a material into the channel region of each of the implanted-channel select cells to increase the threshold voltage of the cells, thereby preventing the implanted channel select cells from conducting when normal operational voltages are applied.Type: GrantFiled: September 24, 1993Date of Patent: June 6, 1995Assignee: National Semiconductor CorporationInventors: Graham Wolstenholme, Albert Bergemont, Etan Shacham