Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

Abstract: Systems, apparatuses, and methods for implementing a combo scheme for direct current (DC) level shifting of signals are disclosed. A receiver circuit receives an input signal on a first interface. The first interface is coupled to a resistor in parallel with a capacitor which passes the input signal to a second interface. Also, the first interface is coupled to a first pair of current sources between ground and a voltage source, and the second interface is coupled to a second pair of current sources between ground and the voltage source. An op-amp drives the current sources based on a difference between a sensed common mode voltage and a reference voltage. Based on this circuit configuration, the receiver circuit is able to prevent baseline wander, perform a DC level shift of the input signal, and achieve linear equalization of the input signal.

Abstract: A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.

Abstract: A clock and data recovery (CDR) circuit operates to recover a clock and sample data from full-rate and sub-rate data signals. The CDR circuit selectively shifts one or more of the sampling clocks based on the rate of a received data signal, facilitating accurate sampling of sub-rate data signals. A masking circuit selectively masks data output bits clocked by a selection of the sampling clocks, thereby outputting relevant sampled data.

Abstract: A data recovery circuit provides compensation for baseline wander exhibited by a data signal. An adaptive equalizer generates a recovered data signal from a data input. A level shifter and low-pass filter provide a compensation signal as a function of the recovered data signal. An adaptation engine adjusts the level of the compensation signal to compensate for baseline wander. The adaptive equalizer generates the recovered data signal as a function of the data input and the compensation signal, thereby providing accurate recovery of the data signal.

Abstract: A data recovery circuit provides compensation for baseline wander exhibited by a data signal. An adaptive equalizer generates a recovered data signal from a data input. A level shifter and low-pass filter provide a compensation signal as a function of the recovered data signal. An adaptation engine adjusts the level of the compensation signal to compensate for baseline wander. The adaptive equalizer generates the recovered data signal as a function of the data input and the compensation signal, thereby providing accurate recovery of the data signal.

Abstract: In an example embodiment, a circuit includes an oscillator providing a set of clock phase signals. A main edge rate controller (ERC) coupled to the oscillator is configured to adjust an edge rate of each clock phase signal of the set of clock phase signals. An interpolator coupled to the main ERC is configured to interpolate the adjusted set of clock phase signals to provide at least one desired phase output signal. An edge rate controller calibrator comprises a ring oscillator including at least three ERCs connected in a loop, a counter configured to count a number of cycles of the ring oscillator over a given period, and a finite state machine (FSM) configured to compare the counter count to a given value corresponding to an operating frequency of the circuit and to adjust operation of the circuit based on the comparison.

Abstract: An improved clock data recovery circuit is provided which provides lower bit error rates and faster locking times. In an embodiment, the circuit includes a voter having one or more voter inputs. The voter may generate up votes indicative of a recovered clock having a negative phase offset relative to a given voter input, or down votes indicative of the recovered clock having a positive phase offset. The circuit may include a comparator configured to output a phase adjustment signal and a tie signal. The circuit may further include an M-depth shift register and a multiplexer configured to select either the phase adjustment signal or an output from the shift register as a multiplexer output. The circuit may further include a flip-flop that generates a phase adjustment output signal. The shift register may receive the phase adjustment output signal at a data input of the shift register.

Abstract: An improved clock data recovery circuit is provided which provides lower bit error rates and faster locking times. In an embodiment, the circuit includes a voter having one or more voter inputs. The voter may generate up votes indicative of a recovered clock having a negative phase offset relative to a given voter input, or down votes indicative of the recovered clock having a positive phase offset. The circuit may include a comparator configured to output a phase adjustment signal and a tie signal. The circuit may further include an M-depth shift register and a multiplexer configured to select either the phase adjustment signal or an output from the shift register as a multiplexer output. The circuit may further include a flip-flop that generates a phase adjustment output signal. The shift register may receive the phase adjustment output signal at a data input of the shift register.

Abstract: A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.

Abstract: A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.

Abstract: A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.

Abstract: A folder common cascode circuit with symmetric parallel signal paths from the differential inputs to the differential outputs provides a low skew, low jitter, low power differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NMOS and PMOS transistor pairs with parallel complementary biasing stacks on the output cascode circuitry maintain symmetrical parallel signal paths, amplification and impedance loading from differential input to differential output. Output voltage translating inverters provide a higher voltage level output signal while maintaining low skew and jitter.

Abstract: A low read current, low power consumption sense amplifier well suited for low frequency RFID systems is disclosed. An MOS transistor receives the read current from a memory cell, typically an EEPROM, and a current mirror is formed by a parallel MOS transistor. The mirror current is integrated on a capacitor after the charge on the capacitor is cleared via a reset pulse. A time period is defined during which the voltage on the capacitor is compared to a second voltage. The second voltage is formed from a reference voltage or from dummy cells, in either case the reference voltage is at about the logic boundary between a one and zero stored in a memory cell. A comparator, with or without input hysteresis, receives the voltage on the capacitor and a second voltage and within the time period, the output state of the comparator indicates the binary contents of the memory cell.

Abstract: A folder common cascode circuit with symmetric parallel signal paths from the differential inputs to the differential outputs provides a low skew, low jitter, low power differential amplifier. The signal paths on either side of the differential amplifier are made equal with equal loads along each path. Pairs of complementary NODS and PODS transistor pairs with parallel complementary biasing stacks on the output cascode circuitry maintain symmetrical parallel signal paths, amplification and impedance loading from differential input to differential output. Output voltage translating inverters provide a higher voltage level output signal while maintaining low skew and jitter.