Patents by Inventor Ethan A. Mirsky
Ethan A. Mirsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10662432Abstract: Methods for making synthetic gene clusters are described.Type: GrantFiled: September 15, 2017Date of Patent: May 26, 2020Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Ethan Mirsky, Karsten Temme, Christopher A. Voigt, Dehua Zhao
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Publication number: 20200115715Abstract: Methods for making synthetic gene clusters are described.Type: ApplicationFiled: October 31, 2019Publication date: April 16, 2020Inventors: Ethan Mirsky, Karsten Temme, Christopher A. Voigt, Dehua Zhao
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Patent number: 9957509Abstract: Methods for making synthetic gene clusters are described.Type: GrantFiled: October 7, 2016Date of Patent: May 1, 2018Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Ethan Mirsky, Karsten Temme, Christopher A. Voigt, Dehua Zhao
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Publication number: 20180073028Abstract: Methods for making synthetic gene clusters are described.Type: ApplicationFiled: September 15, 2017Publication date: March 15, 2018Inventors: Ethan Mirsky, Karsten Temme, Christopher A. Voigt, Dehua Zhao
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Publication number: 20170152519Abstract: Methods for making synthetic gene clusters are described.Type: ApplicationFiled: October 7, 2016Publication date: June 1, 2017Inventors: Ethan Mirsky, Karsten Temme, Christopher A. Voigt, Dehua Zhao
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Patent number: 9512431Abstract: Methods for making synthetic gene clusters are described.Type: GrantFiled: June 14, 2012Date of Patent: December 6, 2016Assignee: The Regents of the University of CaliforniaInventors: Ethan Mirsky, Karsten Temme, Christopher A. Voigt, Dehua Zhao
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Publication number: 20140329326Abstract: Methods for making synthetic gene clusters are described.Type: ApplicationFiled: June 14, 2012Publication date: November 6, 2014Applicant: The Regents of the University of CaliforniaInventors: Ethan Mirsky, Karsten Temme, Christopher A. Voigt, Dehua Zhao
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Patent number: 7464251Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to the saturation signal.Type: GrantFiled: February 27, 2003Date of Patent: December 9, 2008Assignee: Broadcom CorporationInventor: Ethan A. Mirsky
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Patent number: 7266672Abstract: A method and an apparatus for retiming in a network of multiple context processing elements in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element.Type: GrantFiled: December 16, 2002Date of Patent: September 4, 2007Assignee: Broadcom CorporationInventors: Ethan Mirsky, Robert French, Ian Eslick
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Patent number: 7188192Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores configuration memory contexts and maintains data of a current configuration. State information is received from at least one other MCPE. A configuration control signal is generated in response to the state information and current configuration data. A MCPE is selected in response to the configuration control signal to control the MCPE. Each MCPE in the networked array has an assigned physical and virtual identification. Data comprising control data, configuration data, an address mask, and a destination identification is transmitted to a MCPE. The transmitted address mask is applied to either a physical or a virtual identification, and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification.Type: GrantFiled: May 3, 2004Date of Patent: March 6, 2007Assignee: Broadcom CorporationInventors: Ethan Mirsky, Robert French, Ian Eslick
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Patent number: 6990566Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs) are described. The method and an apparatus is capable of selectively transmitting data over a bidirectional shared bus network including a plurality of channels between pairs of MCPEs in the networked array. The method and an apparatus then selectively transmits a sideband bit indicating a direction in which the data is transmitted in the shared bus network.Type: GrantFiled: April 20, 2004Date of Patent: January 24, 2006Assignee: Broadcom CorporationInventors: Ethan Mirsky, Robert French, Ian Eslick
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Patent number: 6976141Abstract: A memory management system provides the ability for multiple requesters to access blocks of memory in a pipelined manner. During a first clock, requests for one or more of the memory blocks are received by the system. A determination is made of whether one of the memory blocks is requested by one or more requests. If the same memory block is requested by two or more requests, the system performs a further determination of which of the requests will be provided to the memory block. The determined request is provided to the memory block on the first clock. During a second clock, the data of the determined request is latched to the memory block and a memory access is initiated. If the request is a write request, the data is written to the memory block. If the request is a read request, then the requested data is retrieved and, on a third clock, the data is driven onto a bus, routed to the determined requester, and available to be latched into the requester on the fourth clock.Type: GrantFiled: November 2, 2001Date of Patent: December 13, 2005Assignee: Broadcom CorporationInventors: Lawrence J. Madar, III, John R. Nickolls, Ethan Mirsky
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Patent number: 6959378Abstract: A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed.Type: GrantFiled: November 2, 2001Date of Patent: October 25, 2005Assignee: Broadcom CorporationInventors: John R. Nickolls, Scott D. Johnson, Mark Williams, Ethan Mirsky, Kambdur Kirthiranjan, Amrit Raj Pant, Lawrence J. Madar, III
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Publication number: 20050038978Abstract: A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed.Type: ApplicationFiled: September 22, 2004Publication date: February 17, 2005Inventors: John Nickolls, Scott Johnson, Mark Williams, Ethan Mirsky, Kambdur Kirthiranjan, Amrit Pant, Lawrence Madar
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Publication number: 20040236815Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs) are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks join at MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 network drivers and switches. In one embodiment, the level 3 network is bidirectional and dynamically routable.Type: ApplicationFiled: April 20, 2004Publication date: November 25, 2004Applicant: BROADCOM CORPORATIONInventors: Ethan Mirsky, Robert French, Ian Eslick
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Publication number: 20040205321Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores configuration memory contexts and maintains data of a current configuration. State information is received from at least one other MCPE. A configuration control signal is generated in response to the state information and current configuration data. A MCPE is selected in response to the configuration control signal to control the MCPE. Each MCPE in the networked array has an assigned physical and virtual identification. Data comprising control data, configuration data, an address mask, and a destination identification is transmitted to a MCPE. The transmitted address mask is applied to either a physical or a virtual identification, and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification.Type: ApplicationFiled: May 3, 2004Publication date: October 14, 2004Applicant: BROADCOM CORPORATIONInventors: Ethan Mirsky, Robert French, Ian Eslick
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Patent number: 6751722Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores configuration memory contexts and maintains data of a current configuration. State information is received from at least one other MCPE. A configuration control signal is generated in response to the state information and current configuration data. A MCPE is selected in response to the configuration control signal to control the MCPE. Each MCPE in the networked array has an assigned physical and virtual identification. Data comprising control data, configuration data, an address mask, and a destination identification is transmitted to a MCPE. The transmitted address mask is applied to either a physical or a virtual identification, and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification.Type: GrantFiled: February 27, 2003Date of Patent: June 15, 2004Assignee: Broadcom CorporationInventors: Ethan Mirsky, Robert French, Ian Eslick
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Patent number: 6745317Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks join at MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 network drivers and switches. In one embodiment, the level 3 network is bidirectional and dynamically routable.Type: GrantFiled: July 30, 1999Date of Patent: June 1, 2004Assignee: Broadcom CorporationInventors: Ethan Mirsky, Robert French, Ian Eslick
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Patent number: 6684318Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.Type: GrantFiled: November 12, 2002Date of Patent: January 27, 2004Assignee: Massachusetts Institute of TechnologyInventors: André DeHon, Ethan Mirsky, Thomas F. Knight, Jr.
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Publication number: 20030200418Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.Type: ApplicationFiled: November 12, 2002Publication date: October 23, 2003Applicant: Massachusetts Institute of TechnologyInventors: Andre DeHon, Ethan Mirsky, Thomas F. Knight,