Abstract: An integrated circuit (IC) package comprises a stack with first and second electronic devices respectively having a first array and a second array of rows and columns of pads bonded to each other. At least one testing structure comprises a first pattern of first pads of the first array, a second pattern of second pads of the second array, and at least four pad-pairs of one of the first pads adjacent to one of the second pads, wherein each pair has different pads than the other pairs. An aligned state of the first and second electronic devices exists wherein each pad-pair has a different offset length separating the first pad from the second pad, and wherein none of the first and second pads of the pairs are electrically connected.

Abstract: The present disclosure is directed to an inspection tool having a probe head with a probe card with a plurality of probes for performing testing, each of the probes being configured with a first end attached to the probe card and a second end for engaging microbumps coupled to a semiconductor die, the plurality of probes including a first set of probes having a first cross-sectional dimension, the first set of probes being arranged in a first set of locations on the probe card, and a second set of probes having a second cross-sectional dimension, the second set of probes being arranged in a second set of locations on the probe card, and a stage for holding the semiconductor die.

Abstract: The present disclosure is directed to an inspection tool having a probe head with a probe card with a plurality of probes for performing testing, each of the probes being configured with a first end attached to the probe card and a second end for engaging microbumps coupled to a semiconductor die, the plurality of probes including a first set of probes having a first cross-sectional dimension, the first set of probes being arranged in a first set of locations on the probe card, and a second set of probes having a second cross-sectional dimension, the second set of probes being arranged in a second set of locations on the probe card, and a stage for holding the semiconductor die.

Abstract: An apparatus includes an input probe configured to be placed on a first cluster of u-bumps disposed on a semiconductor die, output probes configured to be respectively placed on multiple clusters of u-bumps disposed on the semiconductor die, the multiple clusters being separately connected to the first cluster. The apparatus further includes a space transformer and printed circuit board (PCB) portion including a current source configured to supply a current to the input probe placed on the first cluster, resistors having a same resistance and being connected to ground, and tester channels at which voltages are respectively measured, the tester channels being respectively connected to ends of the output probes respectively placed on the multiple clusters and being respectively connected to the resistors. The apparatus further includes a processor configured to determine whether the input probe is properly aligned with the first cluster, based on the measured voltages.

Abstract: Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.

Abstract: Disclosed herein are apparatuses and methods for mitigating sticking of units-under-test (UUTs). For example, in some embodiments, a probe card may include a probe landing pad, a guide plate having a hole therein, and a pushing mechanism. The pushing mechanism may include a pusher needle and a pusher needle support, the pusher needle support may be between the probe landing pad and the guide plate, and the pusher needle support may be controllable to cause the pusher needle to extend and retract through the hole in the guide plate.

Abstract: An apparatus for testing a die can comprise a first printed circuit board (PCB), a space transformer, and a plurality of probes. The first PCB can be configured to connect to a second PCB. The space transformer can be attached to the PCB. The space transformer can include a plurality of traces. Each of the plurality of probes can be connected to one of the plurality of traces.

Abstract: A test system includes a test printed circuit board (PCB), a flip chip package mounted on the PCB, one or more test probes coupled to the flip chip package and a first integrated circuit (IC) coupled to the test probes to enable testing of the first IC using electrical circuitry of the flip chip package.

Abstract: An apparatus for testing a die can comprise a first printed circuit board (PCB), a space transformer, and a plurality of probes. The first PCB can be configured to connect to a second PCB. The space transformer can be attached to the PCB. The space transformer can include a plurality of traces. Each of the plurality of probes can be connected to one of the plurality of traces. The plurality of probes can be arranged in a pattern having a pitch less than 65 microns.

Abstract: A test system includes a test printed circuit board (PCB), a flip chip package mounted on the PCB, one or more test probes coupled to the flip chip package and a first integrated circuit (IC) coupled to the test probes to enable testing of the first IC using electrical circuitry of the flip chip package.