Patents by Inventor Ethan Harrison Cannon
Ethan Harrison Cannon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8035200Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P?N junction diode. The P?N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.Type: GrantFiled: June 3, 2010Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: John M. Aitken, Ethan Harrison Cannon, Alvin Wayne Strong
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Patent number: 7989865Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.Type: GrantFiled: August 28, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: John Edward Barth, Jr., Kerry Bernstein, Ethan Harrison Cannon, Francis Roger White
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Publication number: 20100237475Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P-N junction diode. The P-N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.Type: ApplicationFiled: June 3, 2010Publication date: September 23, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John M. Aitken, Ethan Harrison Cannon, Alvin Wayne Strong
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Patent number: 7750406Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.Type: GrantFiled: October 24, 2007Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Ethan Harrison Cannon, Toshiharu Furukawa, John Gerard Gaudiello, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Jack Allan Mandelman, William Robert Tonti
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Patent number: 7736915Abstract: A method for neutralizing trapped charges in a buried oxide layer. The method includes providing a semiconductor structure which includes (a) a semiconductor layer, (b) a charge accumulation layer on top of the semiconductor layer, and (c) a doped region in direct physical contact with the semiconductor layer, wherein the charge accumulation layer comprises trapped charges of a first sign, and wherein the doped region and the semiconductor layer form a P-N junction diode. Next, free charges are generated in the P-N junction diode, wherein the free charges are of a second sign opposite to the first sign. Next, the free charges are accelerated towards the charge accumulation layer, resulting in some of the free charges entering the charge accumulation layer and neutralizing some of the trapped charges in the charge accumulation layer.Type: GrantFiled: February 21, 2006Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: John M. Aitken, Ethan Harrison Cannon, Alvin Wayne Strong
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Publication number: 20100052026Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.Type: ApplicationFiled: August 28, 2008Publication date: March 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Edward Barth, JR., Kerry Bernstein, Ethan Harrison Cannon, Francis Roger White
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Patent number: 7651902Abstract: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.Type: GrantFiled: April 20, 2007Date of Patent: January 26, 2010Assignee: International Business Machines CorporationInventors: Ethan Harrison Cannon, Toshiharu Furukawa, John Gerard Gaudiello, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, III, Jack Allan Mandelman, William Robert Tonti
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Publication number: 20090113357Abstract: A method, device and system for monitoring ionizing radiation, and design structures for ionizing radiation monitoring devices. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.Type: ApplicationFiled: October 25, 2007Publication date: April 30, 2009Inventors: Wagdi William Abadeer, Ethan Harrison Cannon, Dennis Thomas Cox, William Robert Tonti
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Patent number: 7473904Abstract: A device and system for monitoring ionizing radiation. The device including: a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and a cathode of the diode coupled to a precharged node of a clocked logic circuit, an output state of the clocked logic circuit responsive a change in state of the precharged node, a state of the precharged node responsive to ionizing radiation induced charge collected by a depletion region of the diode and collected in the cathode.Type: GrantFiled: February 11, 2008Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Wagdi William Abadeer, Ethan Harrison Cannon, Dennis Thomas Cox, William Robert Tonti
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Publication number: 20090001481Abstract: A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity.Type: ApplicationFiled: June 26, 2007Publication date: January 1, 2009Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, David Vaclav Horak, Jack A. Mandelman, William Robert Tonti
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Publication number: 20080258181Abstract: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, John Gerard Gaudiello, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, Jack Allan Mandelman, William Robert Tonti
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Publication number: 20080258222Abstract: Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes devices formed in a hybrid substrate characterized by semiconductor islands of different crystal orientations. An insulating layer divides the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.Type: ApplicationFiled: October 24, 2007Publication date: October 23, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan Harrison Cannon, Toshiharu Furukawa, John Gerard Gaudiello, Mark Charles Hakey, Steven John Holmes, David Vaclav Horak, Charles William Koburger, Jack Allan Mandelman, William Robert Tonti
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Publication number: 20080242016Abstract: Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.Type: ApplicationFiled: May 8, 2008Publication date: October 2, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan Harrison Cannon, Toshiharu Furukawa, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, Jimmy Konstantinos Kontos, Jack Allan Mandelman, William Robert Tonti
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Publication number: 20080203492Abstract: Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.Type: ApplicationFiled: May 8, 2008Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ethan Harrison Cannon, Toshiharu Furukawa, Mark Charles Hakey, David Vaclav Horak, Charles William Koburger, Jimmy Konstantinos Kontos, Jack Allan Mandelman, William Robert Tonti
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Patent number: 7397692Abstract: An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.Type: GrantFiled: December 19, 2006Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Ethan Harrison Cannon, Toshiharu Furukawa, David Vaclav Horak, Charles William Koburger, III, Jack A. Mandelman
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Publication number: 20080144348Abstract: An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.Type: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, David Vaclav Horak, Charles William Koburger, Jack A. Mandelman
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Patent number: 7385275Abstract: A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel region formed from a portion of a silicon substrate, a gate dielectric formed over the channel region, and a gate electrode comprising a bottom surface in direct physical contact with the gate dielectric. A top surface of the channel region is located within a first plane and the bottom surface of the gate electrode is located within a second plane. The STI structure comprises a conductive STI fill structure. A top surface of the conductive STI fill structure is above the first plane by a first distance D1 and is above the second plane by a second distance D2 that is less than D1.Type: GrantFiled: February 15, 2006Date of Patent: June 10, 2008Assignee: International Business Machines CorporationInventors: Ethan Harrison Cannon, Shunhua Thomas Chang, Toshiharu Furukawa, David Vaclav Horak, Charles William Koburger, III
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Publication number: 20080128629Abstract: A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.Type: ApplicationFiled: February 11, 2008Publication date: June 5, 2008Inventors: Wagdi William Abadeer, Ethan Harrison Cannon, Dennis Thomas Cox, William Robert Tonti
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Patent number: 7375339Abstract: A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.Type: GrantFiled: April 28, 2006Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: Wagdi William Abadeer, Ethan Harrison Cannon, Dennis Thomas Cox, William Robert Tonti